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| author | Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> | 2011-08-26 08:44:21 +0000 |
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| committer | Ramana Radhakrishnan <ramana@gcc.gnu.org> | 2011-08-26 08:44:21 +0000 |
| commit | 58a2bda0e5d919cec4491a7fed2bd88cfb7411b9 (patch) | |
| tree | 1bbe4367a05f26cb1ee7bf45be18c49ff51a9a64 /gcc | |
| parent | e4680a3ba0fc1ce14de13efe1762b9b7582d251f (diff) | |
| download | gcc-58a2bda0e5d919cec4491a7fed2bd88cfb7411b9.zip gcc-58a2bda0e5d919cec4491a7fed2bd88cfb7411b9.tar.gz gcc-58a2bda0e5d919cec4491a7fed2bd88cfb7411b9.tar.bz2 | |
Fix scheduling descriptions for smull, smmul and friends on Cortex-A9.
From-SVN: r178098
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/config/arm/cortex-a9.md | 21 |
2 files changed, 22 insertions, 7 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index df92093..c4274b0 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2011-08-26 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> + + * config/arm/cortex-a9.md ("cortex_a9_mult_long"): New. + ("cortex_a9_multiply_long"): New and use above. Handle all + long multiply cases. + ("cortex_a9_multiply"): Handle smmul and smmulr. + ("cortex_a9_mac"): Handle smmla. + 2011-08-25 Richard Henderson <rth@redhat.com> PR 50132 diff --git a/gcc/config/arm/cortex-a9.md b/gcc/config/arm/cortex-a9.md index b74ace8..12c19ef 100644 --- a/gcc/config/arm/cortex-a9.md +++ b/gcc/config/arm/cortex-a9.md @@ -68,7 +68,8 @@ cortex_a9_p1_e2 + cortex_a9_p0_e1 + cortex_a9_p1_e1") "cortex_a9_mac_m1*2, cortex_a9_mac_m2, cortex_a9_p0_wb") (define_reservation "cortex_a9_mac" "cortex_a9_multcycle1*2 ,cortex_a9_mac_m2, cortex_a9_p0_wb") - +(define_reservation "cortex_a9_mult_long" + "cortex_a9_mac_m1*3, cortex_a9_mac_m2, cortex_a9_p0_wb") ;; Issue at the same time along the load store pipeline and ;; the VFP / Neon pipeline is not possible. @@ -139,29 +140,35 @@ cortex_a9_p1_e2 + cortex_a9_p0_e1 + cortex_a9_p1_e1") (eq_attr "insn" "smlaxy")) "cortex_a9_mac16") - (define_insn_reservation "cortex_a9_multiply" 4 (and (eq_attr "tune" "cortexa9") - (eq_attr "insn" "mul")) + (eq_attr "insn" "mul,smmul,smmulr")) "cortex_a9_mult") (define_insn_reservation "cortex_a9_mac" 4 (and (eq_attr "tune" "cortexa9") - (eq_attr "insn" "mla")) + (eq_attr "insn" "mla,smmla")) "cortex_a9_mac") +(define_insn_reservation "cortex_a9_multiply_long" 5 + (and (eq_attr "tune" "cortexa9") + (eq_attr "insn" "smull,umull,smulls,umulls,smlal,smlals,umlal,umlals")) + "cortex_a9_mult_long") + ;; An instruction with a result in E2 can be forwarded ;; to E2 or E1 or M1 or the load store unit in the next cycle. (define_bypass 1 "cortex_a9_dp" "cortex_a9_dp_shift, cortex_a9_multiply, cortex_a9_load1_2, cortex_a9_dp, cortex_a9_store1_2, - cortex_a9_mult16, cortex_a9_mac16, cortex_a9_mac, cortex_a9_store3_4, cortex_a9_load3_4") + cortex_a9_mult16, cortex_a9_mac16, cortex_a9_mac, cortex_a9_store3_4, cortex_a9_load3_4, + cortex_a9_multiply_long") (define_bypass 2 "cortex_a9_dp_shift" "cortex_a9_dp_shift, cortex_a9_multiply, cortex_a9_load1_2, cortex_a9_dp, cortex_a9_store1_2, - cortex_a9_mult16, cortex_a9_mac16, cortex_a9_mac, cortex_a9_store3_4, cortex_a9_load3_4") + cortex_a9_mult16, cortex_a9_mac16, cortex_a9_mac, cortex_a9_store3_4, cortex_a9_load3_4, + cortex_a9_multiply_long") ;; An instruction in the load store pipeline can provide ;; read access to a DP instruction in the P0 default pipeline @@ -212,7 +219,7 @@ cortex_a9_store3_4, cortex_a9_store1_2, cortex_a9_load3_4") (define_bypass 1 "cortex_a9_fps" - "cortex_a9_fadd, cortex_a9_fps, cortex_a9_fcmp, cortex_a9_dp, cortex_a9_dp_shift, cortex_a9_multiply") + "cortex_a9_fadd, cortex_a9_fps, cortex_a9_fcmp, cortex_a9_dp, cortex_a9_dp_shift, cortex_a9_multiply, cortex_a9_multiply_long") ;; Scheduling on the FP_ADD pipeline. (define_reservation "ca9fp_add" "ca9_issue_vfp_neon + ca9fp_add1, ca9fp_add2, ca9fp_add3, ca9fp_add4") |