c4x.c: Added space after negation operator.

	* config/c4x/c4x.c: Added space after negation operator.
	* config/c4x/c4x.h: Likewise.
	* config/c4x/c4x.md: Likewise.

From-SVN: r24555

4 files changed, 185 insertions, 179 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index b1c9ac2..54197b2 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+Thu Jan  7 23:54:05 1999  Michael Hayes  <m.hayes@elec.canterbury.ac.nz>
+
+	* config/c4x/c4x.c: Added space after negation operator.
+	* config/c4x/c4x.h: Likewise.
+	* config/c4x/c4x.md: Likewise.
+
 Thu Jan  7 23:39:27 1999  Michael Hayes  <m.hayes@elec.canterbury.ac.nz>
 
 	* config/c4x/c4x.c (c4x_preferred_reload_class): Always return class.
diff --git a/gcc/config/c4x/c4x.c b/gcc/config/c4x/c4x.c
index ef49bed..5a6ff22 100644
--- a/gcc/config/c4x/c4x.c
+++ b/gcc/config/c4x/c4x.c
@@ -204,12 +204,12 @@ c4x_override_options ()
 
   /* We should phase out the following at some stage.
      This provides compatibility with the old -mno-rptb option.  */
-  if (!TARGET_RPTB && flag_branch_on_count_reg)
+  if (! TARGET_RPTB && flag_branch_on_count_reg)
     flag_branch_on_count_reg = 0;
 
   /* We should phase out the following at some stage.
      This provides compatibility with the old -mno-aliases option.  */
-  if (!TARGET_ALIASES && !flag_argument_noalias)
+  if (! TARGET_ALIASES && ! flag_argument_noalias)
     flag_argument_noalias = 1;
 }
 
@@ -282,7 +282,7 @@ c4x_output_ascii (stream, ptr, len)
     }
   if (s)
     {
-      if (!first)
+      if (! first)
 	fputc (',', stream);
 
       sbuf[s] = 0;
@@ -418,12 +418,12 @@ c4x_init_cumulative_args (cum, fntype, libname)
 
 	  /* If the last arg doesn't have void type then we have
 	     variable arguments.  */
-	  if (!next_param)
+	  if (! next_param)
 	    cum->var = 1;
 
 	  if ((mode = TYPE_MODE (type)))
 	    {
-	      if (!MUST_PASS_IN_STACK (mode, type))
+	      if (! MUST_PASS_IN_STACK (mode, type))
 		{
 		  /* Look for float, double, or long double argument.  */
 		  if (mode == QFmode || mode == HFmode)
@@ -460,10 +460,10 @@ c4x_function_arg_advance (cum, mode, type, named)
   if (TARGET_DEBUG)
     fprintf (stderr, "c4x_function_adv(mode=%s, named=%d)\n\n",
 	     GET_MODE_NAME (mode), named);
-  if (!TARGET_MEMPARM 
+  if (! TARGET_MEMPARM 
       && named
       && type
-      && !MUST_PASS_IN_STACK (mode, type))
+      && ! MUST_PASS_IN_STACK (mode, type))
     {
       /* Look for float, double, or long double argument.  */
       if (mode == QFmode || mode == HFmode)
@@ -472,7 +472,7 @@ c4x_function_arg_advance (cum, mode, type, named)
       else if (mode == QImode || mode == Pmode)
 	cum->ints++;
     }
-  else if (!TARGET_MEMPARM && !type)
+  else if (! TARGET_MEMPARM && ! type)
     {
       /* Handle libcall arguments.  */
       if (mode == QFmode || mode == HFmode)
@@ -506,7 +506,7 @@ c4x_function_arg (cum, mode, type, named)
 {
   int reg = 0;			/* default to passing argument on stack */
 
-  if (!cum->init)
+  if (! cum->init)
     {
       /* We can handle at most 2 floats in R2, R3 */
       cum->maxfloats = (cum->floats > 2) ? 2 : cum->floats;
@@ -517,17 +517,17 @@ c4x_function_arg (cum, mode, type, named)
 	6 - cum->maxfloats : cum->ints;
 
       /* If there is no prototype, assume all the arguments are integers. */
-      if (!cum->prototype)
+      if (! cum->prototype)
 	cum->maxints = 6;
 
       cum->ints = cum->floats = 0;
       cum->init = 1;
     }
 
-  if (!TARGET_MEMPARM 
+  if (! TARGET_MEMPARM 
       && named 
       && type
-      && !MUST_PASS_IN_STACK (mode, type))
+      && ! MUST_PASS_IN_STACK (mode, type))
     {
       /* Look for float, double, or long double argument.  */
       if (mode == QFmode || mode == HFmode)
@@ -542,7 +542,7 @@ c4x_function_arg (cum, mode, type, named)
 	    reg = c4x_int_reglist[cum->maxfloats][cum->ints];
 	}
     }
-  else if (!TARGET_MEMPARM && !type)
+  else if (! TARGET_MEMPARM && ! type)
     {
       /* We could use a different argument calling model for libcalls,
          since we're only calling functions in libgcc.  Thus we could
@@ -587,7 +587,7 @@ c4x_isr_reg_used_p (regno)
      We'll only save if for the big memory model or if
      we're paranoid. ;-)  */
   if (IS_DP_REG (regno))
-    return !TARGET_SMALL || TARGET_PARANOID;
+    return ! TARGET_SMALL || TARGET_PARANOID;
 
   /* Only save/restore regs in leaf function that are used.  */
   if (c4x_leaf_function)
@@ -774,7 +774,7 @@ c4x_function_prologue (file, size)
 
       for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
 	{
-	  if (regs_ever_live[regno] && !call_used_regs[regno])
+	  if (regs_ever_live[regno] && ! call_used_regs[regno])
 	    {
 	      if ((regno == R6_REGNO) || (regno == R7_REGNO))
 		{
@@ -783,7 +783,7 @@ c4x_function_prologue (file, size)
 		    fprintf (file, "\tpush\t%s\n", reg_names[regno]);
 		  fprintf (file, "\tpushf\t%s\n", float_reg_names[regno]);
 		}
-	      else if ((!dont_push_ar3) || (regno != AR3_REGNO))
+	      else if ((! dont_push_ar3) || (regno != AR3_REGNO))
 		{
 		  fprintf (file, "\tpush\t%s\n", reg_names[regno]);
 		}
@@ -832,7 +832,7 @@ c4x_function_epilogue (file, size)
     {
       for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; --regno)
 	{
-	  if (!c4x_isr_reg_used_p (regno))
+	  if (! c4x_isr_reg_used_p (regno))
 	    continue;
 	  if (IS_EXT_REG (regno))
 	    fprintf (file, "\tpopf\t%s\n", float_reg_names[regno]);
@@ -887,8 +887,8 @@ c4x_function_epilogue (file, size)
          registers.  */
       for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno--)
 	{
-	  if ((regs_ever_live[regno] && !call_used_regs[regno])
-	      && ((!dont_pop_ar3) || (regno != AR3_REGNO)))
+	  if ((regs_ever_live[regno] && ! call_used_regs[regno])
+	      && ((! dont_pop_ar3) || (regno != AR3_REGNO)))
 	    {
 	      restore_count++;
 	      if (TARGET_PRESERVE_FLOAT
@@ -921,7 +921,7 @@ c4x_function_epilogue (file, size)
          where required.  */
       for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno--)
 	{
-	  if (regs_ever_live[regno] && !call_used_regs[regno])
+	  if (regs_ever_live[regno] && ! call_used_regs[regno])
 	    {
 	      if (regno == AR3_REGNO && dont_pop_ar3)
 		continue;
@@ -988,7 +988,7 @@ c4x_function_epilogue (file, size)
 	  fprintf (file, "\tsubi\t%d,sp\n", size);
 	}
 
-      if (!delayed_jump)
+      if (! delayed_jump)
 	fprintf (file, "\trets\n");
     }
 }
@@ -999,16 +999,16 @@ c4x_null_epilogue_p ()
   int regno;
 
   if (reload_completed
-      && !c4x_assembler_function_p ()
-      && !c4x_interrupt_function_p ()
-      && !current_function_calls_alloca
-      && !current_function_args_size
-      && !(profile_block_flag == 2)
-      && !(optimize < 2)
-      && !get_frame_size ())
+      && ! c4x_assembler_function_p ()
+      && ! c4x_interrupt_function_p ()
+      && ! current_function_calls_alloca
+      && ! current_function_args_size
+      && ! (profile_block_flag == 2)
+      && ! (optimize < 2)
+      && ! get_frame_size ())
     {
       for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno--)
-	if (regs_ever_live[regno] && !call_used_regs[regno]
+	if (regs_ever_live[regno] && ! call_used_regs[regno]
 	    && (regno != AR3_REGNO))
 	  return 0;
       return 1;
@@ -1148,7 +1148,7 @@ c4x_check_legit_addr (mode, addr, strict)
     case PRE_INC:
     case POST_INC:
       base = XEXP (addr, 0);
-      if (!REG_P (base))
+      if (! REG_P (base))
 	return 0;
       break;
 
@@ -1161,7 +1161,7 @@ c4x_check_legit_addr (mode, addr, strict)
 	if (mode != QImode && mode != QFmode)
 	  return 0;
 
-	if (!REG_P (op0) 
+	if (! REG_P (op0) 
 	    || (GET_CODE (op1) != PLUS && GET_CODE (op1) != MINUS))
 	  return 0;
 	base = XEXP (op1, 0);
@@ -1268,9 +1268,9 @@ c4x_check_legit_addr (mode, addr, strict)
       /* Handle DP based stuff.  */
       if (REGNO (base) == DP_REGNO)
 	return 1;
-      if (strict && !REGNO_OK_FOR_BASE_P (REGNO (base)))
+      if (strict && ! REGNO_OK_FOR_BASE_P (REGNO (base)))
 	return 0;
-      else if (!strict && !IS_ADDR_OR_PSEUDO_REGNO (base))
+      else if (! strict && ! IS_ADDR_OR_PSEUDO_REGNO (base))
 	return 0;
     }
 
@@ -1279,9 +1279,9 @@ c4x_check_legit_addr (mode, addr, strict)
     {
       if (GET_CODE (indx) != REG)
 	return 0;
-      if (strict && !REGNO_OK_FOR_INDEX_P (REGNO (indx)))
+      if (strict && ! REGNO_OK_FOR_INDEX_P (REGNO (indx)))
 	return 0;
-      else if (!strict && !IS_INDEX_OR_PSEUDO_REGNO (indx))
+      else if (! strict && ! IS_INDEX_OR_PSEUDO_REGNO (indx))
 	return 0;
     }
 
@@ -1293,12 +1293,12 @@ c4x_check_legit_addr (mode, addr, strict)
       if (mode == HImode || mode == HFmode)
 	{
 	  /* The offset displacement must be legitimate.  */
-	  if (!IS_DISP8_OFF_CONST (INTVAL (disp)))
+	  if (! IS_DISP8_OFF_CONST (INTVAL (disp)))
 	    return 0;
 	}
       else
 	{
-	  if (!IS_DISP8_CONST (INTVAL (disp)))
+	  if (! IS_DISP8_CONST (INTVAL (disp)))
 	    return 0;
 	}
       /* Can't add an index with a disp.  */
@@ -1380,7 +1380,7 @@ rtx addr;
 	    if (IS_DISP1_CONST (INTVAL (op1)))
 	      return 1;
 
-	    if (!TARGET_C3X && IS_UINT5_CONST (INTVAL (op1)))
+	    if (! TARGET_C3X && IS_UINT5_CONST (INTVAL (op1)))
 	      return 2;
 
 	    return 3;
@@ -1426,8 +1426,8 @@ c4x_output_cbranch (form, seq)
   if (final_sequence)
     {
       delay = XVECEXP (final_sequence, 0, 1);
-      delayed = !INSN_ANNULLED_BRANCH_P (seq);
-      annultrue = INSN_ANNULLED_BRANCH_P (seq) && !INSN_FROM_TARGET_P (delay);
+      delayed = ! INSN_ANNULLED_BRANCH_P (seq);
+      annultrue = INSN_ANNULLED_BRANCH_P (seq) && ! INSN_FROM_TARGET_P (delay);
       annulfalse = INSN_ANNULLED_BRANCH_P (seq) && INSN_FROM_TARGET_P (delay);
     }
   strcpy (str, form);
@@ -1510,7 +1510,7 @@ c4x_print_operand (file, op, letter)
       return;
 
     case 'K':			/* generate ldp(k) if direct address */
-      if (!TARGET_SMALL
+      if (! TARGET_SMALL
 	  && code == MEM
 	  && GET_CODE (XEXP (op, 0)) == PLUS
 	  && GET_CODE(XEXP (XEXP (op, 0), 0)) == REG
@@ -1527,7 +1527,7 @@ c4x_print_operand (file, op, letter)
       return;
 
     case 'M':			/* generate ldp(k) if direct address */
-      if (!TARGET_SMALL		/* only used in asm statements */
+      if (! TARGET_SMALL		/* only used in asm statements */
 	  && code == MEM
 	  && (GET_CODE (XEXP (op, 0)) == CONST
 	      || GET_CODE (XEXP (op, 0)) == SYMBOL_REF))
@@ -1769,7 +1769,7 @@ c4x_print_operand_address (file, addr)
     case CONST:
     case SYMBOL_REF:
     case LABEL_REF:
-      if (!SYMBOL_REF_FLAG (addr))
+      if (! SYMBOL_REF_FLAG (addr))
 	fprintf (file, "@");
       output_addr_const (file, addr);
       SYMBOL_REF_FLAG (addr) = 0;
@@ -1849,7 +1849,7 @@ c4x_scan_for_ldp (newop, insn, operand0)
 
 	case CONST:
 	case SYMBOL_REF:
-	  if (!TARGET_C3X && !TARGET_SMALL
+	  if (! TARGET_C3X && ! TARGET_SMALL
 	      && recog_memoized (insn) == CODE_FOR_movqi_noclobber
 	      && ((addr = find_reg_note (insn, REG_EQUAL, NULL_RTX))
 		  || (addr = find_reg_note (insn, REG_EQUIV, NULL_RTX)))
@@ -1888,7 +1888,7 @@ c4x_scan_for_ldp (newop, insn, operand0)
 		  return 1;
 		}
 	    }
-	  if (!TARGET_SMALL)
+	  if (! TARGET_SMALL)
 	    emit_insn_before (gen_set_ldp (gen_rtx_REG (Pmode, DP_REGNO),
 					   operand), insn);
 
@@ -1942,7 +1942,7 @@ c4x_scan_for_ldp (newop, insn, operand0)
 					      gen_rtx_REG (Pmode, DP_REGNO)),
 					  op0));
       
-      if (!TARGET_SMALL)
+      if (! TARGET_SMALL)
 	emit_insn_before (gen_set_ldp_use (gen_rtx_REG (Pmode, DP_REGNO),
 					   *newop, operand), insn);
       return 0;
@@ -2048,7 +2048,7 @@ c4x_rptb_insert (insn)
   for (; insn; insn = PREV_INSN (insn))
     if (insn == start_label)
       break;
-  if (!insn)
+  if (! insn)
     fatal_insn ("c4x_rptb_insert: Cannot find start label", start_label);
 
   /* We'll have to update the basic blocks.  */
@@ -2092,7 +2092,7 @@ c4x_process_after_reload (first)
 	     is a chance that we might be accessing memory across a
 	     page boundary.  */
 
-	  if (!TARGET_SMALL)
+	  if (! TARGET_SMALL)
 	    {
 	      char *template;
 
@@ -2263,7 +2263,7 @@ c4x_Q_constraint (op)
 	rtx op0 = XEXP (op, 0);
 	rtx op1 = XEXP (op, 1);
 
-	if (!REG_P (op0))
+	if (! REG_P (op0))
 	  return 0;
 
 	if (REG_P (op1))
@@ -2310,7 +2310,7 @@ c4x_R_constraint (op)
 	rtx op0 = XEXP (op, 0);
 	rtx op1 = XEXP (op, 1);
 
-	if (!REG_P (op0))
+	if (! REG_P (op0))
 	  return 0;
 
 	if (GET_CODE (op1) != CONST_INT)
@@ -2417,7 +2417,7 @@ c4x_S_constraint (op)
 	if (REG_P (op1))
 	  return 1;
 
-	if (GET_CODE (op1) != CONST_INT)
+	if (GET_CODE (op1) ! = CONST_INT)
 	  return 0;
 	
 	/* HImode and HFmode must be offsettable.  */
@@ -2686,7 +2686,7 @@ not_modify_reg (op, mode)
 	rtx op0 = XEXP (op, 0);
 	rtx op1 = XEXP (op, 1);
 
-	if (!REG_P (op0))
+	if (! REG_P (op0))
 	  return 0;
 	
 	if (REG_P (op1) || GET_CODE (op1) == CONST_INT)
@@ -2719,7 +2719,7 @@ r0r1_reg_operand (op, mode)
      rtx op;
      enum machine_mode mode;
 {
-  if (!register_operand (op, mode))
+  if (! register_operand (op, mode))
     return 0;
   if (GET_CODE (op) == SUBREG)
     op = SUBREG_REG (op);
@@ -2734,7 +2734,7 @@ r2r3_reg_operand (op, mode)
      rtx op;
      enum machine_mode mode;
 {
-  if (!register_operand (op, mode))
+  if (! register_operand (op, mode))
     return 0;
   if (GET_CODE (op) == SUBREG)
     op = SUBREG_REG (op);
@@ -2749,7 +2749,7 @@ ext_low_reg_operand (op, mode)
      rtx op;
      enum machine_mode mode;
 {
-  if (!register_operand (op, mode))
+  if (! register_operand (op, mode))
     return 0;
   if (GET_CODE (op) == SUBREG)
     op = SUBREG_REG (op);
@@ -2764,11 +2764,11 @@ ext_reg_operand (op, mode)
      rtx op;
      enum machine_mode mode;
 {
-  if (!register_operand (op, mode))
+  if (! register_operand (op, mode))
     return 0;
   if (GET_CODE (op) == SUBREG)
     op = SUBREG_REG (op);
-  if (!REG_P (op))
+  if (! REG_P (op))
     return 0;
   return IS_EXT_OR_PSEUDO_REGNO (op);
 }
@@ -2781,7 +2781,7 @@ std_reg_operand (op, mode)
      rtx op;
      enum machine_mode mode;
 {
-  if (!register_operand (op, mode))
+  if (! register_operand (op, mode))
     return 0;
   if (GET_CODE (op) == SUBREG)
     op = SUBREG_REG (op);
@@ -2796,7 +2796,7 @@ addr_reg_operand (op, mode)
      rtx op;
      enum machine_mode mode;
 {
-  if (!register_operand (op, mode))
+  if (! register_operand (op, mode))
     return 0;
   return c4x_a_register (op);
 }
@@ -2809,7 +2809,7 @@ index_reg_operand (op, mode)
      rtx op;
      enum machine_mode mode;
 {
-  if (!register_operand (op, mode))
+  if (! register_operand (op, mode))
     return 0;
   if (GET_CODE (op) == SUBREG)
     op = SUBREG_REG (op);
@@ -3137,7 +3137,7 @@ c4x_address_conflict (op0, op1, store0, store1)
 	 have an aliased address if both locations are not marked
 	 volatile, it is probably safer to flag a potential conflict
 	 if either location is volatile.  */
-      if (!flag_argument_noalias)
+      if (! flag_argument_noalias)
 	{
 	  if (MEM_VOLATILE_P (op0) || MEM_VOLATILE_P (op1))
 	    return 1;
@@ -3156,7 +3156,7 @@ c4x_address_conflict (op0, op1, store0, store1)
   /* It might be too confusing for GCC if we have use a base register
      with a side effect and a memory reference using the same register
      in parallel.  */
-  if (!TARGET_DEVEL && base0 == base1 && (incdec0 || incdec1))
+  if (! TARGET_DEVEL && base0 == base1 && (incdec0 || incdec1))
     return 1;
 
   /* We can not optimize the case where op1 and op2 refer to the same
@@ -3228,22 +3228,22 @@ valid_parallel_load_store (operands, mode)
   if (GET_CODE (op0) == REG && GET_CODE (op2) == REG)
     return (REGNO (op0) != REGNO (op2))
       && GET_CODE (op1) == MEM && GET_CODE (op3) == MEM
-      && !c4x_address_conflict (op1, op3, 0, 0);
+      && ! c4x_address_conflict (op1, op3, 0, 0);
 
   /* STI||STI  */
   if (GET_CODE (op1) == REG && GET_CODE (op3) == REG)
     return GET_CODE (op0) == MEM && GET_CODE (op2) == MEM
-      && !c4x_address_conflict (op0, op2, 1, 1);
+      && ! c4x_address_conflict (op0, op2, 1, 1);
 
   /* LDI||STI  */
   if (GET_CODE (op0) == REG && GET_CODE (op3) == REG)
     return GET_CODE (op1) == MEM && GET_CODE (op2) == MEM
-      && !c4x_address_conflict (op1, op2, 0, 1);
+      && ! c4x_address_conflict (op1, op2, 0, 1);
 
   /* STI||LDI  */
   if (GET_CODE (op1) == REG && GET_CODE (op2) == REG)
     return GET_CODE (op0) == MEM && GET_CODE (op3) == MEM
-      && !c4x_address_conflict (op0, op3, 1, 0);
+      && ! c4x_address_conflict (op0, op3, 1, 0);
 
   return 0;
 }
@@ -3426,7 +3426,7 @@ c4x_valid_operands (code, operands, mode, force)
 	  break;
 	  
 	case CONST_DOUBLE:
-	  if (!c4x_H_constant (op2))
+	  if (! c4x_H_constant (op2))
 	    return 0;
 	  break;
 
@@ -3446,7 +3446,7 @@ c4x_valid_operands (code, operands, mode, force)
       
       /* Check that we have a valid destination register for a two operand
 	 instruction.  */
-      return !force || code == COMPARE || REGNO (op1) == REGNO (operands[0]);
+      return ! force || code == COMPARE || REGNO (op1) == REGNO (operands[0]);
     }
 
   /* We assume MINUS is commutative since the subtract patterns
@@ -3466,7 +3466,7 @@ c4x_valid_operands (code, operands, mode, force)
       break;
       
     case CONST_DOUBLE:
-      if (!c4x_H_constant (op1))
+      if (! c4x_H_constant (op1))
 	return 0;
       break;
 
@@ -3486,7 +3486,7 @@ c4x_valid_operands (code, operands, mode, force)
       
   /* Check that we have a valid destination register for a two operand
      instruction.  */
-  return !force || REGNO (op1) == REGNO (operands[0]);
+  return ! force || REGNO (op1) == REGNO (operands[0]);
 }
 
 
@@ -3504,7 +3504,7 @@ int valid_operands (code, operands, mode)
      operands for an insn when not optimizing.  The problem only rarely
      occurs, for example with the C-torture program DFcmp.c  */
 
-  return !optimize || c4x_valid_operands (code, operands, mode, 0);
+  return ! optimize || c4x_valid_operands (code, operands, mode, 0);
 }
 
 
@@ -3531,17 +3531,17 @@ legitimize_operands (code, operands, mode)
 	 the cost mechanism doesn't allow us to look at the other
 	 operand to decide whether the constant is expensive.  */
       
-      if (!reload_in_progress
+      if (! reload_in_progress
 	  && TARGET_HOIST
 	  && optimize > 0
 	  && ((GET_CODE (operands[1]) == CONST_INT 
-	       && !c4x_J_constant (operands[1])
+	       && ! c4x_J_constant (operands[1])
 	       && INTVAL (operands[1]) != 0)
 	      || GET_CODE (operands[1]) == CONST_DOUBLE))
 	operands[1] = force_reg (mode, operands[1]);
       
-      if (!reload_in_progress
-          && !c4x_valid_operands (code, operands, mode, 0))
+      if (! reload_in_progress
+          && ! c4x_valid_operands (code, operands, mode, 0))
 	operands[0] = force_reg (mode, operands[0]);
       return 1;
     }
@@ -3549,11 +3549,11 @@ legitimize_operands (code, operands, mode)
   /* We cannot do this for ADDI/SUBI insns since we will
      defeat the flow pass from finding autoincrement addressing
      opportunities.  */
-  if (!reload_in_progress
-      && !((code == PLUS || code == MINUS) && mode == Pmode)
+  if (! reload_in_progress
+      && ! ((code == PLUS || code == MINUS) && mode == Pmode)
       && (TARGET_HOIST && optimize > 1
        && ((GET_CODE (operands[2]) == CONST_INT 
-	    && !c4x_J_constant (operands[2])
+	    && ! c4x_J_constant (operands[2])
 	    && INTVAL (operands[2]) != 0)
 	   || GET_CODE (operands[2]) == CONST_DOUBLE)))
     operands[2] = force_reg (mode, operands[2]);
@@ -3568,8 +3568,8 @@ legitimize_operands (code, operands, mode)
      Note that expand_binops will not try to load an expensive constant
      into a register if it is used within a loop for a shift insn.  */
   
-  if (!reload_in_progress
-      && !c4x_valid_operands (code, operands, mode, TARGET_FORCE))
+  if (! reload_in_progress
+      && ! c4x_valid_operands (code, operands, mode, TARGET_FORCE))
     {
       /* If the operand combination is invalid, we force operand1 into a
          register, preventing reload from having doing to do this at a
@@ -3583,7 +3583,7 @@ legitimize_operands (code, operands, mode)
       else
 	{
 	  /* Just in case...  */
-	  if (!c4x_valid_operands (code, operands, mode, 0))
+	  if (! c4x_valid_operands (code, operands, mode, 0))
 	    operands[2] = force_reg (mode, operands[2]);
 	}
     }
@@ -3987,7 +3987,7 @@ c4x_handle_pragma (p_getc, p_ungetc, pname)
 
   c = p_getc ();
   while (c == ' ' || c == '\t') c = p_getc ();
-  if (!(isalpha(c) || c == '_' || c == '$' || c == '@'))
+  if (! (isalpha(c) || c == '_' || c == '$' || c == '@'))
     return 0;
 
   i = 0;
@@ -4090,8 +4090,8 @@ c4x_check_attribute(attrib, list, decl, attributes)
      tree list, decl, *attributes;
 {
   while (list != NULL_TREE
-         && IDENTIFIER_POINTER (TREE_PURPOSE (list)) !=
-	 IDENTIFIER_POINTER (DECL_NAME (decl)))
+         && IDENTIFIER_POINTER (TREE_PURPOSE (list))
+	 != IDENTIFIER_POINTER (DECL_NAME (decl)))
     list = TREE_CHAIN(list);
   if (list)
     *attributes = chainon (*attributes,
@@ -4212,7 +4212,7 @@ c4x_adjust_cost (insn, link, dep_insn, cost)
 {
   /* Don't worry about this until we know what registers have been
      assigned.  */
-  if (!reload_completed)
+  if (! reload_completed)
     return 0;
 
   /* How do we handle dependencies where a read followed by another
diff --git a/gcc/config/c4x/c4x.h b/gcc/config/c4x/c4x.h
index b229551..a2053d3 100644
--- a/gcc/config/c4x/c4x.h
+++ b/gcc/config/c4x/c4x.h
@@ -238,7 +238,7 @@ extern int target_flags;
 #define TARGET_RPTB		(target_flags & RPTB_FLAG \
 				 && optimize >= 2)
 #define TARGET_BK		(target_flags & BK_FLAG)
-#define TARGET_DB		(!TARGET_C3X || (target_flags & DB_FLAG))
+#define TARGET_DB		(! TARGET_C3X || (target_flags & DB_FLAG))
 #define TARGET_DEBUG		(target_flags & DEBUG_FLAG)
 #define TARGET_HOIST		(target_flags & HOIST_FLAG)
 #define TARGET_LOOP_UNSIGNED	(target_flags & LOOP_UNSIGNED_FLAG)
@@ -418,7 +418,7 @@ extern void c4x_optimization_options ();
 
 /* Extended precision registers (high set) */
 
-#define IS_EXT_HIGH_REG(r)         (!TARGET_C3X \
+#define IS_EXT_HIGH_REG(r)         (! TARGET_C3X \
 			            && ((r) >= R8_REGNO) && ((r) <= R11_REGNO))
 /* Address registers */
 
@@ -512,7 +512,7 @@ extern void c4x_optimization_options ();
 
 #define CONDITIONAL_REGISTER_USAGE			\
   {							\
-    if (!TARGET_BK)					\
+    if (! TARGET_BK)					\
       {							\
 	fixed_regs[BK_REGNO] = 1;			\
         call_used_regs[BK_REGNO] = 1;			\
@@ -813,7 +813,7 @@ c4x_secondary_memory_needed(CLASS1, CLASS2, MODE)
 
 #define IS_NOT_UINT16_CONST(VAL) IS_UINT16_CONST(~(VAL))	/* 'N' */
 
-#define IS_HIGH_CONST(VAL) (!TARGET_C3X && (((VAL) & 0xffff) == 0)) /* 'O' */
+#define IS_HIGH_CONST(VAL) (! TARGET_C3X && (((VAL) & 0xffff) == 0)) /* 'O' */
 
 
 #define IS_DISP1_CONST(VAL) (((VAL) <= 1) && ((VAL) >= -1)) /* 'S' */
@@ -828,10 +828,10 @@ c4x_secondary_memory_needed(CLASS1, CLASS2, MODE)
 
 #define CONST_OK_FOR_LETTER_P(VAL, C)					\
         ( ((C) == 'I') ? (IS_INT16_CONST (VAL))				\
-	: ((C) == 'J') ? (!TARGET_C3X && IS_INT8_CONST (VAL))		\
-	: ((C) == 'K') ? (!TARGET_C3X && IS_INT5_CONST (VAL))		\
+	: ((C) == 'J') ? (! TARGET_C3X && IS_INT8_CONST (VAL))		\
+	: ((C) == 'K') ? (! TARGET_C3X && IS_INT5_CONST (VAL))		\
         : ((C) == 'L') ? (IS_UINT16_CONST (VAL))			\
-	: ((C) == 'M') ? (!TARGET_C3X && IS_UINT8_CONST (VAL))		\
+	: ((C) == 'M') ? (! TARGET_C3X && IS_UINT8_CONST (VAL))		\
 	: ((C) == 'N') ? (IS_NOT_UINT16_CONST (VAL))		        \
 	: ((C) == 'O') ? (IS_HIGH_CONST (VAL))			        \
         : 0 )	
@@ -990,7 +990,7 @@ c4x_secondary_memory_needed(CLASS1, CLASS2, MODE)
  int regno;							\
  int offset = 0;						\
   for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)	\
-    if (regs_ever_live[regno] && !call_used_regs[regno])	\
+    if (regs_ever_live[regno] && ! call_used_regs[regno])	\
       offset += TARGET_PRESERVE_FLOAT				\
 		&& ((regno == R6_REGNO) || (regno == R7_REGNO)) \
 		? 2 : 1;					\
@@ -1002,7 +1002,7 @@ c4x_secondary_memory_needed(CLASS1, CLASS2, MODE)
   {{ FRAME_POINTER_REGNUM, FRAME_POINTER_REGNUM }}
 
 #define	CAN_ELIMINATE(FROM, TO)					\
-  (!(((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
+  (! (((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
   || ((FROM) == FRAME_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM)))
 
 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET)	 	\
@@ -1010,7 +1010,7 @@ c4x_secondary_memory_needed(CLASS1, CLASS2, MODE)
  int regno;							\
  int offset = 0;						\
   for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)	\
-    if (regs_ever_live[regno] && !call_used_regs[regno])	\
+    if (regs_ever_live[regno] && ! call_used_regs[regno])	\
       offset += TARGET_PRESERVE_FLOAT				\
 		&& ((regno == R6_REGNO) || (regno == R7_REGNO)) \
 		? 2 : 1;					\
@@ -1108,7 +1108,7 @@ extern struct rtx_def *c4x_function_arg();
    MSBs of the address.  This is not supported by the TI assembler.  */
 
 #define FUNCTION_PROFILER(FILE, LABELNO) 			\
-     if (!TARGET_C3X)						\
+     if (! TARGET_C3X)						\
      {								\
 	fprintf (FILE, "\tpush\tar2\n");			\
 	fprintf (FILE, "\tldhi\t^LP%d,ar2\n", (LABELNO));	\
@@ -1158,7 +1158,7 @@ extern struct rtx_def *c4x_function_arg();
 #define FUNCTION_BLOCK_PROFILER(FILE, BLOCKNO) 			\
   if (profile_block_flag == 2)					\
     {								\
-      if (!TARGET_C3X)						\
+      if (! TARGET_C3X)						\
       {								\
 	fprintf (FILE, "\tpush\tst\n");				\
 	fprintf (FILE, "\tpush\tar2\n");			\
@@ -1205,7 +1205,7 @@ extern struct rtx_def *c4x_function_arg();
     }								\
   else								\
     {								\
-      if (!TARGET_C3X)						\
+      if (! TARGET_C3X)						\
       {								\
 	fprintf (FILE, "\tpush\tst\n");				\
 	fprintf (FILE, "\tpush\tar2\n");			\
@@ -1237,7 +1237,7 @@ extern struct rtx_def *c4x_function_arg();
 #define BLOCK_PROFILER(FILE, BLOCKNO) 				\
   if (profile_block_flag == 2)					\
     {								\
-      if (!TARGET_C3X)						\
+      if (! TARGET_C3X)						\
       {								\
 	fprintf (FILE, "\tpush\tst\n");				\
 	fprintf (FILE, "\tpush\tar2\n");			\
@@ -1293,7 +1293,7 @@ extern struct rtx_def *c4x_function_arg();
     }								\
   else								\
     {								\
-      if (!TARGET_C3X)						\
+      if (! TARGET_C3X)						\
       {								\
 	fprintf (FILE, "\tpush\tar2\n");			\
 	fprintf (FILE, "\tpush\tar0\n");			\
@@ -1830,7 +1830,7 @@ void									\
 const_section ()							\
 {									\
   extern void text_section();						\
-  if (!USE_CONST_SECTION)						\
+  if (! USE_CONST_SECTION)						\
     text_section();							\
   else if (in_section != in_const)					\
     {									\
@@ -1910,10 +1910,10 @@ dtors_section ()							\
   else if (TREE_CODE (DECL) == VAR_DECL)				\
     {									\
       if ((0 && RELOC)	/* should be (flag_pic && RELOC) */		\
-	  || !TREE_READONLY (DECL) || TREE_SIDE_EFFECTS (DECL)		\
-	  || !DECL_INITIAL (DECL)					\
+	  || ! TREE_READONLY (DECL) || TREE_SIDE_EFFECTS (DECL)		\
+	  || ! DECL_INITIAL (DECL)					\
 	  || (DECL_INITIAL (DECL) != error_mark_node			\
-	      && !TREE_CONSTANT (DECL_INITIAL (DECL))))			\
+	      && ! TREE_CONSTANT (DECL_INITIAL (DECL))))			\
 	data_section ();						\
       else								\
 	const_section ();						\
@@ -1965,7 +1965,7 @@ dtors_section ()							\
    may have quietly changed this register on the sly. */
 
 #define ASM_IDENTIFY_GCC(FILE) \
-    if (!TARGET_TI) fputs ("gcc2_compiled.:\n", FILE);	\
+    if (! TARGET_TI) fputs ("gcc2_compiled.:\n", FILE);	\
       fputs ("\t.data\ndata_sec:\n", FILE);
 
 #define ASM_COMMENT_START	";"
diff --git a/gcc/config/c4x/c4x.md b/gcc/config/c4x/c4x.md
index 96672ab..fd565a3 100644
--- a/gcc/config/c4x/c4x.md
+++ b/gcc/config/c4x/c4x.md
@@ -1092,7 +1092,7 @@
 (define_insn "set_ldp"
   [(set (match_operand:QI 0 "dp_reg_operand" "=z")
         (high:QI (match_operand:QI 1 "" "")))]
-  "!TARGET_SMALL"
+  "! TARGET_SMALL"
   "* return (TARGET_C3X) ? \"ldp\\t%A1\" : \"ldpk\\t%A1\";"
   [(set_attr "type" "ldp")])
 
@@ -1105,7 +1105,7 @@
   [(parallel [(set (match_operand:QI 0 "dp_reg_operand" "=z")
                    (high:QI (match_operand:QI 1 "" "")))
               (use (match_operand 2 "" ""))])]
-  "!TARGET_SMALL"
+  "! TARGET_SMALL"
   "* return (TARGET_C3X) ? \"ldp\\t%A1\" : \"ldpk\\t%A1\";"
   [(set_attr "type" "ldp")])
 
@@ -1113,7 +1113,7 @@
   [(parallel [(set (match_operand:QI 0 "std_reg_operand" "=c")
                    (high:QI (match_operand:QI 1 "" "")))
               (use (match_operand 2 "" ""))])]
-  "!TARGET_C3X && !TARGET_SMALL"
+  "! TARGET_C3X && ! TARGET_SMALL"
   "ldhi\\t^%H1,%0"
   [(set_attr "type" "unary")])
 
@@ -1123,7 +1123,7 @@
                            (and:QI (match_operand:QI 1 "" "")
                                    (const_int 65535))))
               (use (match_operand 2 "" ""))])]
-  "!TARGET_C3X && !TARGET_SMALL"
+  "! TARGET_C3X && ! TARGET_SMALL"
   "or\\t#%H1,%0"
   [(set_attr "type" "unary")])
 
@@ -1137,7 +1137,7 @@
 (define_insn "*movqi_stik"
   [(set (match_operand:QI 0 "memory_operand" "=m")
         (match_operand:QI 1 "stik_const_operand" "K"))]
-  "!TARGET_C3X"
+  "! TARGET_C3X"
   "stik\\t%1,%0"
   [(set_attr "type" "store")])
 
@@ -1152,7 +1152,7 @@
    if (which_alternative == 2)
      return \"sti\\t%1,%0\";
 
-   if (!TARGET_C3X && which_alternative == 3)
+   if (! TARGET_C3X && which_alternative == 3)
      {
        operands[1] = GEN_INT ((INTVAL (operands[1]) >> 16) & 0xffff);
        return \"ldhi\\t%1,%0\";
@@ -1160,7 +1160,7 @@
 
    /* The lda instruction cannot use the same register as source
       and destination.  */
-   if (!TARGET_C3X && which_alternative == 1
+   if (! TARGET_C3X && which_alternative == 1
        && (   IS_ADDR_REG (REGNO (operands[0]))
            || IS_INDEX_REG (REGNO (operands[0]))
            || IS_SP_REG (REGNO (operands[0])))
@@ -1230,20 +1230,20 @@
    /* We shouldn't have to do this, since reload is supposed to
       be able to do this if we have a memory constraint.  */
    if (CONSTANT_P (operands[1])
-       && !const_operand (operands[1], QImode))
+       && ! const_operand (operands[1], QImode))
      {
         operands[1] = force_const_mem (QImode, operands[1]);
-        if (!memory_address_p (QImode, XEXP (operands[1], 0))
-            && !reload_in_progress)
+        if (! memory_address_p (QImode, XEXP (operands[1], 0))
+            && ! reload_in_progress)
           operands[1] = change_address (operands[1], QImode,
                                         XEXP (operands[1], 0));
      }
 
-   if (!reload_in_progress
-       && !reg_operand (operands[0], QImode) 
-       && !reg_operand (operands[1], QImode)
-       && !(stik_const_operand (operands[1], QImode) 
-            && !push_operand (operands[0], QImode)))
+   if (! reload_in_progress
+       && ! reg_operand (operands[0], QImode) 
+       && ! reg_operand (operands[1], QImode)
+       && ! (stik_const_operand (operands[1], QImode) 
+            && ! push_operand (operands[0], QImode)))
      operands[1] = force_reg (QImode, operands[1]);")
 
 (define_insn "*movqi_update"
@@ -2051,7 +2051,7 @@
            (sign_extend:HI (match_operand:QI 2 "src_operand" "JR,rS<>,g,JR,rS<>,g")))
       (const_int 32))))
    (clobber (reg:CC_NOOV 21))]
-  "!TARGET_C3X && valid_operands (MULT, operands, QImode)"
+  "! TARGET_C3X && valid_operands (MULT, operands, QImode)"
   "@
    mpyshi3\\t%2,%1,%0
    mpyshi3\\t%2,%1,%0
@@ -2092,7 +2092,7 @@
            (zero_extend:HI (match_operand:QI 2 "lsrc_operand" "JR,rS<>,g,JR,rS<>,g")))
           (const_int 32))))
    (clobber (reg:CC_NOOV 21))]
-  "!TARGET_C3X && valid_operands (MULT, operands, QImode)"
+  "! TARGET_C3X && valid_operands (MULT, operands, QImode)"
   "@
    mpyuhi3\\t%2,%1,%0
    mpyuhi3\\t%2,%1,%0
@@ -2675,7 +2675,7 @@
                                     (match_operand:QI 2 "const_int_operand" "")
                                     (match_operand:QI 3 "const_int_operand" "")))
               (clobber (reg:CC 21))])]
- "!TARGET_C3X"
+ "! TARGET_C3X"
  "if ((INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16)
       || (INTVAL (operands[3]) % INTVAL (operands[2]) != 0))
         FAIL;
@@ -2687,7 +2687,7 @@
                          (match_operand:QI 2 "const_int_operand" "n,n")
                          (match_operand:QI 3 "const_int_operand" "n,n")))
    (clobber (reg:CC 21))]
-  "!TARGET_C3X
+  "! TARGET_C3X
    && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
    && (INTVAL (operands[3]) % INTVAL (operands[2]) == 0)"
   "*
@@ -2709,7 +2709,7 @@
                                      (match_operand:QI 3 "const_int_operand" "n"))
    		    (const_int 0)))
    (clobber (match_scratch:QI 0 "=d"))]
-  "!TARGET_C3X
+  "! TARGET_C3X
    && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
    && (INTVAL (operands[3]) % INTVAL (operands[2]) == 0)"
   "*
@@ -2734,7 +2734,7 @@
         (sign_extract:QI (match_dup 1)
                          (match_dup 2)
                          (match_dup 3)))]
-  "!TARGET_C3X
+  "! TARGET_C3X
    && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
    && (INTVAL (operands[3]) % INTVAL (operands[2]) == 0)"
   "*
@@ -2758,7 +2758,7 @@
                                     (match_operand:QI 2 "const_int_operand" "")
                                     (match_operand:QI 3 "const_int_operand" "")))
               (clobber (reg:CC 21))])]
- "!TARGET_C3X"
+ "! TARGET_C3X"
  "if ((INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16)
       || (INTVAL (operands[3]) % INTVAL (operands[2]) != 0))
         FAIL;
@@ -2770,7 +2770,7 @@
                          (match_operand:QI 2 "const_int_operand" "n,n")
                          (match_operand:QI 3 "const_int_operand" "n,n")))
    (clobber (reg:CC 21))]
-  "!TARGET_C3X
+  "! TARGET_C3X
    && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
    && (INTVAL (operands[3]) % INTVAL (operands[2]) == 0)"
   "*
@@ -2792,7 +2792,7 @@
                                      (match_operand:QI 3 "const_int_operand" "n"))
    		    (const_int 0)))
    (clobber (match_scratch:QI 0 "=d"))]
-  "!TARGET_C3X
+  "! TARGET_C3X
    && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
    && (INTVAL (operands[3]) % INTVAL (operands[2]) == 0)"
   "*
@@ -2817,7 +2817,7 @@
         (zero_extract:QI (match_dup 1)
                          (match_dup 2)
                          (match_dup 3)))]
-  "!TARGET_C3X
+  "! TARGET_C3X
    && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
    && (INTVAL (operands[3]) % INTVAL (operands[2]) == 0)"
   "*
@@ -2841,8 +2841,8 @@
                                     (match_operand:QI 2 "const_int_operand" ""))
                    (match_operand:QI 3 "src_operand" ""))
               (clobber (reg:CC 21))])]
- "!TARGET_C3X"
- "if (!(((INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
+ "! TARGET_C3X"
+ "if (! (((INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
          && (INTVAL (operands[2]) % INTVAL (operands[1]) == 0))
         || (INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8)))
     FAIL;
@@ -2854,7 +2854,7 @@
                          (match_operand:QI 2 "const_int_operand" "n,n"))
         (match_operand:QI 3 "src_operand" "g,g"))
    (clobber (reg:CC 21))]
-  "!TARGET_C3X
+  "! TARGET_C3X
    && (((INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
         && (INTVAL (operands[2]) % INTVAL (operands[1]) == 0))
        || (INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8))"
@@ -2882,7 +2882,7 @@
 	      (clobber (reg:CC 21))])
    (set (reg:CC 21)
         (compare:CC (match_dup 0) (const_int 0)))]
-  "!TARGET_C3X
+  "! TARGET_C3X
    && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
    && (INTVAL (operands[2]) % INTVAL (operands[1]) == 0)"
   "*
@@ -2914,18 +2914,18 @@
         (match_operand:QF 1 "src_operand" ""))]
  ""
  "
-  if (CONSTANT_P (operands[1]) && !const_operand (operands[1], QFmode))
+  if (CONSTANT_P (operands[1]) && ! const_operand (operands[1], QFmode))
     {
       operands[1] = force_const_mem (QFmode, operands[1]);
-      if (!memory_address_p (QFmode, XEXP (operands[1], 0))
-          && !reload_in_progress)
+      if (! memory_address_p (QFmode, XEXP (operands[1], 0))
+          && ! reload_in_progress)
         operands[1] = change_address (operands[1], QFmode,
                                       XEXP (operands[1], 0));
     }
 
-  if (!reload_in_progress
-      && !reg_operand (operands[0], QFmode)
-      && !reg_operand (operands[1], QFmode))
+  if (! reload_in_progress
+      && ! reg_operand (operands[0], QFmode)
+      && ! reg_operand (operands[1], QFmode))
     operands[1] = force_reg (QFmode, operands[1]);
  ")
 
@@ -3237,7 +3237,7 @@
   [(set (match_operand:QF 0 "reg_operand" "=f")
         (unspec [(match_operand:QF 1 "src_operand" "fmH")] 5))
    (clobber (reg:CC_NOOV 21))]
-  "!TARGET_C3X"
+  "! TARGET_C3X"
   "rcpf\\t%1,%0"
   [(set_attr "type" "unarycc")])
 
@@ -3248,7 +3248,7 @@
   [(set (match_operand:QF 0 "reg_operand" "=f")
         (unspec [(match_operand:QF 1 "src_operand" "fmH")] 10))
    (clobber (reg:CC_NOOV 21))]
-  "!TARGET_C3X"
+  "! TARGET_C3X"
   "rsqrf\\t%1,%0"
   [(set_attr "type" "unarycc")])
 
@@ -3259,7 +3259,7 @@
   [(set (match_operand:QF 0 "reg_operand" "=f")
         (unspec [(match_operand:QF 1 "src_operand" "fmH")] 6))
    (clobber (reg:CC_NOOV 21))]
-  "!TARGET_C3X"
+  "! TARGET_C3X"
   "rnd\\t%1,%0"
   [(set_attr "type" "unarycc")])
 
@@ -3292,9 +3292,9 @@
    (parallel [(set (match_operand:QF 0 "reg_operand" "")
 	           (unspec [(match_dup 4)] 6))
 	      (clobber (reg:CC_NOOV 21))])]
-  "!TARGET_C3X"
-  "if (!reload_in_progress
-       && !reg_operand (operands[1], QFmode))
+  "! TARGET_C3X"
+  "if (! reload_in_progress
+       && ! reg_operand (operands[1], QFmode))
      operands[1] = force_reg (QFmode, operands[1]);
    operands[2] = gen_reg_rtx (QFmode);
    operands[3] = gen_reg_rtx (QFmode);
@@ -3309,7 +3309,7 @@
                    (sqrt:QF (match_operand:QF 1 "src_operand" "")))
               (clobber (reg:CC 21))])]
   ""
-  "if (TARGET_C3X || !TARGET_INLINE)
+  "if (TARGET_C3X || ! TARGET_INLINE)
      FAIL;
    else
      {
@@ -3537,9 +3537,9 @@
    (parallel [(set (match_operand:QF 0 "reg_operand" "")
 	           (unspec [(match_dup 3)] 6))
 	      (clobber (reg:CC_NOOV 21))])]
-  "!TARGET_C3X"
-  "if (!reload_in_progress
-      && !reg_operand (operands[2], QFmode))
+  "! TARGET_C3X"
+  "if (! reload_in_progress
+      && ! reg_operand (operands[2], QFmode))
      operands[2] = force_reg (QFmode, operands[2]);
    operands[3] = gen_reg_rtx (QFmode);
    operands[4] = gen_reg_rtx (QFmode);
@@ -3551,7 +3551,7 @@
                             (match_operand:QF 2 "src_operand" "")))
               (clobber (reg:CC 21))])]
   ""
-  "if (TARGET_C3X || !TARGET_INLINE)
+  "if (TARGET_C3X || ! TARGET_INLINE)
      {
        c4x_emit_libcall3 (DIVQF3_LIBCALL, DIV, QFmode, operands);
        DONE;
@@ -4339,7 +4339,7 @@
   (clobber (reg:QI 31))]
   ;; Operand 1 not really used on the C4x.
 
-  "!TARGET_C3X"
+  "! TARGET_C3X"
   "*
    if (which_alternative == 0)
      {
@@ -4386,7 +4386,7 @@
   (clobber (reg:QI 31))]
   ;; Operand 0 and 2 not really used in the C30 instruction.
 
-  "!TARGET_C3X"
+  "! TARGET_C3X"
   "*
    if (which_alternative == 0)
      {
@@ -4553,7 +4553,7 @@
    (use (label_ref (match_operand 1 "" "")))]
   ""
   "*
-   return !final_sequence && c4x_rptb_rpts_p (insn, operands[0])
+   return ! final_sequence && c4x_rptb_rpts_p (insn, operands[0])
 	 ? \"rpts\\trc\" : \"rptb%#\\t%l1-1\";
   "
   [(set_attr "type" "repeat_top")])
@@ -4809,15 +4809,15 @@
  "if (CONSTANT_P (operands[1]))
     {
       operands[1] = force_const_mem (HFmode, operands[1]); 
-      if (!memory_address_p (HFmode, XEXP (operands[1], 0))
-          && !reload_in_progress)
+      if (! memory_address_p (HFmode, XEXP (operands[1], 0))
+          && ! reload_in_progress)
         operands[1] = change_address (operands[1], HFmode,
                                       XEXP (operands[1], 0));
      }
 
   /* Memory to memory copies must go through a register.  */
   if (GET_CODE (operands[1]) == MEM && GET_CODE (operands[0]) == MEM
-      && !reload_in_progress)
+      && ! reload_in_progress)
     operands[1] = force_reg (HFmode, operands[1]); 
 ")
 
@@ -5104,7 +5104,7 @@
   [(set (match_operand:HF 0 "reg_operand" "=h")
         (unspec [(match_operand:HF 1 "reg_or_const_operand" "hH")] 5))
    (clobber (reg:CC_NOOV 21))]
-  "!TARGET_C3X"
+  "! TARGET_C3X"
   "rcpf\\t%1,%0"
   [(set_attr "type" "unarycc")])
 
@@ -5115,7 +5115,7 @@
   [(set (match_operand:HF 0 "reg_operand" "=h")
         (unspec [(match_operand:HF 1 "reg_or_const_operand" "hH")] 10))
    (clobber (reg:CC_NOOV 21))]
-  "!TARGET_C3X"
+  "! TARGET_C3X"
   "rsqrf\\t%1,%0"
   [(set_attr "type" "unarycc")])
 
@@ -5126,7 +5126,7 @@
   [(set (match_operand:HF 0 "reg_operand" "=h")
         (unspec [(match_operand:HF 1 "reg_or_const_operand" "hH")] 6))
    (clobber (reg:CC_NOOV 21))]
-  "!TARGET_C3X"
+  "! TARGET_C3X"
   "rnd\\t%1,%0"
   [(set_attr "type" "unarycc")])
 
@@ -5157,7 +5157,7 @@
    (parallel [(set (match_operand:HF 0 "reg_operand" "")
 		   (mult:HF (match_dup 2) (match_dup 1)))
 	      (clobber (reg:CC_NOOV 21))])]
-  "!TARGET_C3X"
+  "! TARGET_C3X"
   "
   operands[2] = gen_reg_rtx (HFmode);
   operands[3] = gen_reg_rtx (HFmode);
@@ -5172,7 +5172,7 @@
                    (sqrt:HF (match_operand:HF 1 "reg_operand" "")))
               (clobber (reg:CC 21))])]
   ""
-  "if (TARGET_C3X || !TARGET_INLINE)
+  "if (TARGET_C3X || ! TARGET_INLINE)
      FAIL;
    else
      {
@@ -5309,7 +5309,7 @@
 		   (mult:HF (match_operand:HF 1 "reg_operand" "")
 	         	    (match_dup 3)))
 	      (clobber (reg:CC_NOOV 21))])]
-  "!TARGET_C3X"
+  "! TARGET_C3X"
   "
   operands[3] = gen_reg_rtx (HFmode);
   operands[4] = gen_reg_rtx (HFmode);
@@ -5322,7 +5322,7 @@
                            (match_operand:HF 2 "reg_operand" "")))
               (clobber (reg:CC 21))])]
   ""
-  "if (TARGET_C3X || !TARGET_INLINE)
+  "if (TARGET_C3X || ! TARGET_INLINE)
      {
        c4x_emit_libcall3 (DIVHF3_LIBCALL, DIV, HFmode, operands);
        DONE;
@@ -5350,15 +5350,15 @@
       /* We don't need to force all constants into memory.
          This could be improved.... */
       operands[1] = force_const_mem (HImode, operands[1]); 
-      if (!memory_address_p (HImode, XEXP (operands[1], 0))
-          && !reload_in_progress)
+      if (! memory_address_p (HImode, XEXP (operands[1], 0))
+          && ! reload_in_progress)
         operands[1] = change_address (operands[1], HImode,
                                       XEXP (operands[1], 0));
      }
 
   /* Memory to memory copies must go through a register.  */
   if (GET_CODE (operands[1]) == MEM && GET_CODE (operands[0]) == MEM
-      && !reload_in_progress)
+      && ! reload_in_progress)
     operands[1] = force_reg (HImode, operands[1]); 
 ")
 
@@ -5411,7 +5411,7 @@
   [(set (match_operand:HI 0 "reg_operand" "=?dc")
         (sign_extend:HI (match_operand:QI 1 "src_operand" "g")))
    (clobber (reg:CC 21))]
-  "reload_completed && !TARGET_C3X"
+  "reload_completed && ! TARGET_C3X"
   [(set (match_dup 2) (match_dup 1))
    (parallel [(set (match_dup 3) (ashiftrt:QI (match_dup 2) (const_int 31)))
               (clobber (reg:CC 21))])]
@@ -5955,7 +5955,7 @@
   [(set (reg:CC 21)
         (compare:CC (match_operand:HI 0 "src_operand" "")
                     (match_operand:HI 1 "src_operand" "")))]
-  "!reload_completed"
+  "! reload_completed"
   [(parallel [(set (reg:CC 21)
                    (unspec [(compare:CC (match_dup 0)
                                         (match_dup 1))] 4))
@@ -5967,7 +5967,7 @@
   [(set (reg:CC_NOOV 21)
         (compare:CC_NOOV (match_operand:HI 0 "src_operand" "")
                          (match_operand:HI 1 "src_operand" "")))]
-  "!reload_completed"
+  "! reload_completed"
   [(parallel [(set (reg:CC_NOOV 21)
                    (unspec [(compare:CC_NOOV (match_dup 0)
                                              (match_dup 1))] 4))
@@ -6191,7 +6191,7 @@
           (plus:QI (match_dup 0)
                    (const_int -1)))
      (clobber (reg:CC_NOOV 21))])]
-  "!c4x_label_conflict (insn, operands[2], operands[1])"
+  "! c4x_label_conflict (insn, operands[2], operands[1])"
   "db%I3\\t%0,%l1\\n\\tb%3\\t%l2")
 
 (define_peephole
@@ -6210,7 +6210,7 @@
           (plus:QI (match_dup 0)
                    (const_int -1)))
      (clobber (reg:CC_NOOV 21))])]
-  "!c4x_label_conflict (insn, operands[2], operands[1])"
+  "! c4x_label_conflict (insn, operands[2], operands[1])"
   "db%I3\\t%0,%l1\\n\\tb%3\\t%l2")
 
 ;
@@ -6248,7 +6248,7 @@
   (set (match_operand:QI 2 "ext_low_reg_operand" "")
        (match_operand:QI 3 "par_ind_operand" ""))]
  "(REGNO (operands[0]) != REGNO (operands[2])) 
-  && !c4x_address_conflict (operands[1], operands[3], 0, 0)"
+  && ! c4x_address_conflict (operands[1], operands[3], 0, 0)"
  "ldi1\\t%1,%0\\n||\\tldi2\\t%3,%2")
 
 ; load occurs before store if 1 and 2 point to same address
@@ -6258,7 +6258,7 @@
   (set (match_operand:QI 2 "par_ind_operand" "")
        (match_operand:QI 3 "ext_low_reg_operand" ""))]
  "(REGNO (operands[0]) != REGNO (operands[3]))
-  && !c4x_address_conflict (operands[1], operands[2], 0, 1)"
+  && ! c4x_address_conflict (operands[1], operands[2], 0, 1)"
  "ldi\\t%1,%0\\n||\\tsti\\t%3,%2")
 
 ; load occurs before store if 0 and 3 point to same address
@@ -6268,7 +6268,7 @@
   (set (match_operand:QI 2 "ext_low_reg_operand" "")
        (match_operand:QI 3 "par_ind_operand" ""))]
  "(REGNO (operands[1]) != REGNO (operands[2]))
-  && !c4x_address_conflict (operands[0], operands[3], 1, 0)"
+  && ! c4x_address_conflict (operands[0], operands[3], 1, 0)"
  "ldi\\t%3,%2\\n||\\tsti\\t%1,%0")
 
 (define_peephole
@@ -6276,7 +6276,7 @@
        (match_operand:QI 1 "ext_low_reg_operand" ""))
   (set (match_operand:QI 2 "par_ind_operand" "")
        (match_operand:QI 3 "ext_low_reg_operand" ""))]
- "!c4x_address_conflict (operands[0], operands[2], 1, 1)"
+ "! c4x_address_conflict (operands[0], operands[2], 1, 1)"
  "sti\\t%1,%0\\n||\\tsti\\t%3,%2")
 
 ; This peephole should be unnecessary with my patches to flow.c
@@ -6297,7 +6297,7 @@
   (set (match_operand:QF 2 "ext_low_reg_operand" "")
        (match_operand:QF 3 "par_ind_operand" ""))]
  "(REGNO (operands[0]) != REGNO (operands[2]))
-  && !c4x_address_conflict (operands[1], operands[3], 0, 1)"
+  && ! c4x_address_conflict (operands[1], operands[3], 0, 1)"
  "ldf1\\t%1,%0\\n||\\tldf2\\t%3,%2")
 
 ; This peephole should be unnecessary with my patches to flow.c
@@ -6325,7 +6325,7 @@
        (match_operand:QF 1 "ext_low_reg_operand" ""))
   (set (match_operand:QF 2 "ext_low_reg_operand" "")
        (match_operand:QF 3 "par_ind_operand" ""))]
- "!c4x_address_conflict (operands[0], operands[3], 1, 1)"
+ "! c4x_address_conflict (operands[0], operands[3], 1, 1)"
  "ldf\\t%3,%2\\n||\\tstf\\t%1,%0")
 
 (define_peephole
@@ -6333,7 +6333,7 @@
        (match_operand:QF 1 "ext_low_reg_operand" ""))
   (set (match_operand:QF 2 "par_ind_operand" "")
        (match_operand:QF 3 "ext_low_reg_operand" ""))]
- "!c4x_address_conflict (operands[0], operands[2], 1, 1)"
+ "! c4x_address_conflict (operands[0], operands[2], 1, 1)"
  "stf1\\t%1,%0\\n||\\tstf2\\t%3,%2")
 
 (define_peephole