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authorMichael Hayes <m.hayes@elec.canterbury.ac.nz>1999-04-01 17:02:51 +0000
committerMichael Hayes <m.hayes@gcc.gnu.org>1999-04-01 17:02:51 +0000
commit4b97aaeb34b0e0dadbd2eced838111fd77b4c0dc (patch)
treea4c904eee8e0704a31d9d9badd85dd038116c659 /gcc
parent8de858c039e88a7957458d6c21ec5545818d634d (diff)
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c4x.md (ashlhi3, [...]): Force operand 1 into a register if shift count not constant.
* config/c4x/c4x.md (ashlhi3, lshrhi3, ashrhi3): Force operand 1 into a register if shift count not constant. (ashlhi3_reg, lshrhi3_reg, ashrhi3_reg): Ensure that operand 1 is a register. From-SVN: r26109
Diffstat (limited to 'gcc')
-rw-r--r--gcc/ChangeLog7
-rw-r--r--gcc/config/c4x/c4x.md26
2 files changed, 23 insertions, 10 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 84a589e..e0e39a6 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+Fri Apr 2 12:58:26 1999 Michael Hayes <m.hayes@elec.canterbury.ac.nz>
+
+ * config/c4x/c4x.md (ashlhi3, lshrhi3, ashrhi3): Force operand 1
+ into a register if shift count not constant.
+ (ashlhi3_reg, lshrhi3_reg, ashrhi3_reg): Ensure that operand 1
+ is a register.
+
Fri Apr 2 12:19:17 1999 Michael Hayes <m.hayes@elec.canterbury.ac.nz>
* config/c4x/c4x.md (*db): Enable pattern if TARGET_LOOP_UNSIGNED
diff --git a/gcc/config/c4x/c4x.md b/gcc/config/c4x/c4x.md
index 6509941..ab96ddd 100644
--- a/gcc/config/c4x/c4x.md
+++ b/gcc/config/c4x/c4x.md
@@ -5791,7 +5791,6 @@
operands[7] = c4x_operand_subword (operands[1], 1, 1, HImode);
operands[8] = c4x_operand_subword (operands[2], 1, 1, HImode);")
-; This should do all the dirty work with define_split
(define_expand "ashlhi3"
[(parallel [(set (match_operand:HI 0 "reg_operand" "")
(ashift:HI (match_operand:HI 1 "src_operand" "")
@@ -5812,14 +5811,17 @@
emit_insn (gen_movqi (op0lo, const0_rtx));
DONE;
}
- emit_insn (gen_ashlhi3_reg (operands[0], operands[1], operands[2]));
- DONE;")
+ if (! REG_P (operands[1]))
+ operands[1] = force_reg (HImode, operands[1]);
+ emit_insn (gen_ashlhi3_reg (operands[0], operands[1], operands[2]));
+ DONE;
+ ")
; %0.lo = %1.lo << %2
; %0.hi = (%1.hi << %2 ) | (%1.lo >> (32 - %2))
; This algorithm should work for shift counts greater than 32
(define_expand "ashlhi3_reg"
- [(use (match_operand:HI 1 "src_operand" ""))
+ [(use (match_operand:HI 1 "reg_operand" ""))
(use (match_operand:HI 0 "reg_operand" ""))
/* If the shift count is greater than 32 this will give zero. */
(parallel [(set (match_dup 7)
@@ -5874,14 +5876,16 @@
emit_insn (gen_movqi (op0hi, const0_rtx));
DONE;
}
- emit_insn (gen_lshrhi3_reg (operands[0], operands[1], operands[2]));
- DONE;")
+ if (! REG_P (operands[1]))
+ operands[1] = force_reg (HImode, operands[1]);
+ emit_insn (gen_lshrhi3_reg (operands[0], operands[1], operands[2]));
+ DONE;")
; %0.hi = %1.hi >> %2
; %0.lo = (%1.lo >> %2 ) | (%1.hi << (32 - %2))
; This algorithm should work for shift counts greater than 32
(define_expand "lshrhi3_reg"
- [(use (match_operand:HI 1 "src_operand" ""))
+ [(use (match_operand:HI 1 "reg_operand" ""))
(use (match_operand:HI 0 "reg_operand" ""))
(parallel [(set (match_dup 11)
(neg:QI (match_operand:QI 2 "reg_operand" "")))
@@ -5942,14 +5946,16 @@
emit_insn (gen_ashrqi3 (op0hi, op1hi, GEN_INT (31)));
DONE;
}
- emit_insn (gen_ashrhi3_reg (operands[0], operands[1], operands[2]));
- DONE;")
+ if (! REG_P (operands[1]))
+ operands[1] = force_reg (HImode, operands[1]);
+ emit_insn (gen_ashrhi3_reg (operands[0], operands[1], operands[2]));
+ DONE;")
; %0.hi = %1.hi >> %2
; %0.lo = (%1.lo >> %2 ) | (%1.hi << (32 - %2))
; This algorithm should work for shift counts greater than 32
(define_expand "ashrhi3_reg"
- [(use (match_operand:HI 1 "src_operand" ""))
+ [(use (match_operand:HI 1 "reg_operand" ""))
(use (match_operand:HI 0 "reg_operand" ""))
(parallel [(set (match_dup 11)
(neg:QI (match_operand:QI 2 "reg_operand" "")))