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| author | Claudiu Zissulescu <claziss@synopsys.com> | 2016-04-28 14:15:06 +0200 |
|---|---|---|
| committer | Claudiu Zissulescu <claziss@gcc.gnu.org> | 2016-04-28 14:15:06 +0200 |
| commit | 4ac2f36e33655a8fae9fe98e07cf5f77564902fc (patch) | |
| tree | d1ede566440a947e60fc459d8577f88db7b53bea /gcc | |
| parent | e54a38e86b29eb062545ed30ab0bda6ebd4c9c33 (diff) | |
| download | gcc-4ac2f36e33655a8fae9fe98e07cf5f77564902fc.zip gcc-4ac2f36e33655a8fae9fe98e07cf5f77564902fc.tar.gz gcc-4ac2f36e33655a8fae9fe98e07cf5f77564902fc.tar.bz2 | |
[ARC] Don't use drsub* instructions when selecting fpuda.
The double precision floating point assist instructions are not
implementing the reverse double subtract instruction (drsub) found in
the FPX extension.
gcc/
2016-04-28 Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc.md (cpu_facility): Add fpx variant.
(subdf3): Prohibit use reverse sub when assist operations option
is enabled.
* config/arc/fpx.md (subdf3_insn, *dsubh_peep2_insn): Allow drsub
instructions only when FPX is enabled.
* testsuite/gcc.target/arc/trsub.c: New test.
From-SVN: r235562
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 9 | ||||
| -rw-r--r-- | gcc/config/arc/arc.md | 8 | ||||
| -rw-r--r-- | gcc/config/arc/fpx.md | 7 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/arc/trsub.c | 10 |
4 files changed, 30 insertions, 4 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index bfe7b83..4025863 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2016-04-28 Claudiu Zissulescu <claziss@synopsys.com> + + * config/arc/arc.md (cpu_facility): Add fpx variant. + (subdf3): Prohibit use reverse sub when assist operations option + is enabled. + * config/arc/fpx.md (subdf3_insn, *dsubh_peep2_insn): Allow drsub + instructions only when FPX is enabled. + * testsuite/gcc.target/arc/trsub.c: New test. + 2016-04-28 Uros Bizjak <ubizjak@gmail.com> * config/i386/i386.md (*fop_<mode>_1_mixed): Do not check for diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index 4a7287b..a58b491 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -270,7 +270,7 @@ - get_attr_length (insn)"))) ; for ARCv2 we need to disable/enable different instruction alternatives -(define_attr "cpu_facility" "std,av1,av2" +(define_attr "cpu_facility" "std,av1,av2,fpx" (const_string "std")) ; We should consider all the instructions enabled until otherwise @@ -282,6 +282,10 @@ (and (eq_attr "cpu_facility" "av2") (not (match_test "TARGET_V2"))) (const_string "no") + + (and (eq_attr "cpu_facility" "fpx") + (match_test "TARGET_FP_DP_AX")) + (const_string "no") ] (const_string "yes"))) @@ -5780,6 +5784,8 @@ " if (TARGET_DPFP) { + if (TARGET_FP_DP_AX && (GET_CODE (operands[1]) == CONST_DOUBLE)) + operands[1] = force_reg (DFmode, operands[1]); if ((GET_CODE (operands[1]) == CONST_DOUBLE) || GET_CODE (operands[2]) == CONST_DOUBLE) { diff --git a/gcc/config/arc/fpx.md b/gcc/config/arc/fpx.md index b790600..2e11157 100644 --- a/gcc/config/arc/fpx.md +++ b/gcc/config/arc/fpx.md @@ -304,7 +304,8 @@ drsubh%F0%F2 0,%H1,%L1 drsubh%F0%F2 0,%3,%L1" [(set_attr "type" "dpfp_addsub") - (set_attr "length" "4,8,4,8")]) + (set_attr "length" "4,8,4,8") + (set_attr "cpu_facility" "*,*,fpx,fpx")]) ;; ;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Peephole for following conversion @@ -613,5 +614,5 @@ drsubh%F0%F2 %H6, %H1, %L1 drsubh%F0%F2 %H6, %3, %L1" [(set_attr "type" "dpfp_addsub") - (set_attr "length" "4,8,4,8")] -) + (set_attr "length" "4,8,4,8") + (set_attr "cpu_facility" "*,*,fpx,fpx")]) diff --git a/gcc/testsuite/gcc.target/arc/trsub.c b/gcc/testsuite/gcc.target/arc/trsub.c new file mode 100644 index 0000000..031935f --- /dev/null +++ b/gcc/testsuite/gcc.target/arc/trsub.c @@ -0,0 +1,10 @@ +/* Tests if we generate rsub instructions when compiling using + floating point assist instructions. */ +/* { dg-do compile } */ +/* { dg-options "-mfpu=fpuda -mcpu=arcem" } */ + +double foo (double a) +{ + return ((double) 0.12 - a); +} +/* { dg-final { scan-assembler-not "drsub.*" } } */ |