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author | Uros Bizjak <uros@gcc.gnu.org> | 2016-08-29 20:58:10 +0200 |
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committer | Uros Bizjak <uros@gcc.gnu.org> | 2016-08-29 20:58:10 +0200 |
commit | 414b7129496a41e3a96220c103fd9f9e8ac0b840 (patch) | |
tree | 993e1eb6ff064045efe4726805d207f2c782e1c3 /gcc | |
parent | 3d06b6f2fd3258e2d9ab18e034f0bacb06a9d062 (diff) | |
download | gcc-414b7129496a41e3a96220c103fd9f9e8ac0b840.zip gcc-414b7129496a41e3a96220c103fd9f9e8ac0b840.tar.gz gcc-414b7129496a41e3a96220c103fd9f9e8ac0b840.tar.bz2 |
re PR target/77403 (assemble failure of vinserti64x4 with -masm=intel)
PR target/77403
* config/i386/sse.md (vec_set_lo_<mode><mask_name>): Fix assembler
template for intel asm dialect.
(vec_set_hi_<mode><mask_name>): Ditto.
testsuite/ChangeLog:
PR target/77403
* gcc.target/i386/pr77403.c: New test.
From-SVN: r239834
Diffstat (limited to 'gcc')
-rw-r--r-- | gcc/ChangeLog | 20 | ||||
-rw-r--r-- | gcc/config/i386/sse.md | 6 | ||||
-rw-r--r-- | gcc/testsuite/ChangeLog | 13 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/i386/pr77403.c | 15 |
4 files changed, 41 insertions, 13 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0e5b3af..065b9a3 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2016-08-29 Uros Bizjak <ubizjak@gmail.com> + + PR target/77403 + * config/i386/sse.md (vec_set_lo_<mode><mask_name>): Fix assembler + template for intel asm dialect. + (vec_set_hi_<mode><mask_name>): Ditto. + 2016-08-29 David Malcolm <dmalcolm@redhat.com> * selftest.h (selftest::fail): Add ATTRIBUTE_NORETURN. @@ -192,7 +199,7 @@ (ipcp_bits_lattice): New class. (ipcp_param_lattice (bits_lattice): New member. (print_all_lattices): Call ipcp_bits_lattice::print. - (set_all_contains_variable): Call ipcp_bits_lattice::set_to_bottom. + (set_all_contains_variable): Call ipcp_bits_lattice::set_to_bottom. (initialize_node_lattices): Likewise. (propagate_bits_accross_jump_function): New function. (propagate_constants_accross_call): Call @@ -220,7 +227,8 @@ (ipa_read_jump_function): Add support for reading streamed ipa_bits. (write_ipcp_transformation_info): Add streaming for ipa_bits summary for ltrans. - (read_ipcp_transfomration_info): Add support for reading streamed ipa_bits. + (read_ipcp_transfomration_info): Add support for reading streamed + ipa_bits. (ipcp_update_bits): New function. (ipcp_transform_function): Call ipcp_update_bits. @@ -393,7 +401,7 @@ * statistics.c (statistics_counter_event): Robustify against NULL current_pass. -2016-08-23 Venkataramanan Kumar +2016-08-23 Venkataramanan Kumar <venkataramanan.kumar@amd.com> * config/i386/i386.c (processor_alias_table): Enable PTA_PRFCHW for targets amdfam10 and barcelona. @@ -1713,9 +1721,9 @@ 2016-08-09 Martin Jambor <mjambor@suse.cz> - PR ipa/71981 - * ipa-polymorphic-call.c (get_dynamic_type): Bail out gracefully - if instance is a MEM_REF. + PR ipa/71981 + * ipa-polymorphic-call.c (get_dynamic_type): Bail out gracefully + if instance is a MEM_REF. 2016-08-09 Uros Bizjak <ubizjak@gmail.com> diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 9a39c74..7e718a0 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -12334,7 +12334,7 @@ (const_int 12) (const_int 13) (const_int 14) (const_int 15)]))))] "TARGET_AVX512DQ" - "vinsert<shuffletype>32x8\t{$0x0, %2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2, $0x0}" + "vinsert<shuffletype>32x8\t{$0x0, %2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2, 0x0}" [(set_attr "type" "sselog") (set_attr "length_immediate" "1") (set_attr "prefix" "evex") @@ -12351,7 +12351,7 @@ (const_int 6) (const_int 7)])) (match_operand:<ssehalfvecmode> 2 "nonimmediate_operand" "vm")))] "TARGET_AVX512DQ" - "vinsert<shuffletype>32x8\t{$0x1, %2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2, $0x1}" + "vinsert<shuffletype>32x8\t{$0x1, %2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2, 0x1}" [(set_attr "type" "sselog") (set_attr "length_immediate" "1") (set_attr "prefix" "evex") @@ -12366,7 +12366,7 @@ (parallel [(const_int 4) (const_int 5) (const_int 6) (const_int 7)]))))] "TARGET_AVX512F" - "vinsert<shuffletype>64x4\t{$0x0, %2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2, $0x0}" + "vinsert<shuffletype>64x4\t{$0x0, %2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2, 0x0}" [(set_attr "type" "sselog") (set_attr "length_immediate" "1") (set_attr "prefix" "evex") diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 3aed281..2a97b4b 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2016-08-29 Uros Bizjak <ubizjak@gmail.com> + + PR target/77403 + * gcc.target/i386/pr77403.c: New test. + 2016-08-29 Marek Polacek <polacek@redhat.com> PR c/77292 @@ -342,10 +347,10 @@ 2016-08-19 Janne Blomqvist <jb@gcc.gnu.org> - * gfortran.dg/random_4.f90: Initialize seed before using, handle - the last special seed value. - * gfortran.dg/random_7.f90: Use size for last array member instead - of hardcoded value. + * gfortran.dg/random_4.f90: Initialize seed before using, handle + the last special seed value. + * gfortran.dg/random_7.f90: Use size for last array member instead + of hardcoded value. 2016-08-19 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org> diff --git a/gcc/testsuite/gcc.target/i386/pr77403.c b/gcc/testsuite/gcc.target/i386/pr77403.c new file mode 100644 index 0000000..9f6775a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr77403.c @@ -0,0 +1,15 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target int128 } */ +/* { dg-require-effective-target avx512f } */ +/* { dg-require-effective-target masm_intel } */ +/* { dg-options "-O -mavx512f -masm=intel" } */ + +typedef __int128 V __attribute__((vector_size(64))); + +V v; + +void +foo() +{ + v ^= (V){1}; +} |