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| author | Kyrylo Tkachov <kyrylo.tkachov@arm.com> | 2016-06-01 10:37:27 +0000 |
|---|---|---|
| committer | Kyrylo Tkachov <ktkachov@gcc.gnu.org> | 2016-06-01 10:37:27 +0000 |
| commit | 39fa4aec86086b874af53424da8a6d4f5217729b (patch) | |
| tree | 24a90875010c1639a83c3e28357d9457481720dd /gcc | |
| parent | a0dfeef505c7d5a619cc91d37acbfb9ea2c7f729 (diff) | |
| download | gcc-39fa4aec86086b874af53424da8a6d4f5217729b.zip gcc-39fa4aec86086b874af53424da8a6d4f5217729b.tar.gz gcc-39fa4aec86086b874af53424da8a6d4f5217729b.tar.bz2 | |
[ARM] Tie operand 1 to operand 0 in AESMC pattern when fusing AES/AESMC
* config/arm/arm.c (arm_fusion_enabled_p): New function.
* config/arm/arm-protos.h (arm_fusion_enabled_p): Declare prototype.
* config/arm/crypto.md (crypto_<crypto_pattern>, CRYPTO_UNARY):
Add "=w,0" alternative. Enable it when AES/AESMC fusion is enabled.
From-SVN: r236982
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/arm/arm-protos.h | 1 | ||||
| -rw-r--r-- | gcc/config/arm/arm.c | 7 | ||||
| -rw-r--r-- | gcc/config/arm/crypto.md | 19 |
4 files changed, 31 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 83a96bd..b9baf4c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2016-06-01 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + * config/arm/arm.c (arm_fusion_enabled_p): New function. + * config/arm/arm-protos.h (arm_fusion_enabled_p): Declare prototype. + * config/arm/crypto.md (crypto_<crypto_pattern>, CRYPTO_UNARY): + Add "=w,0" alternative. Enable it when AES/AESMC fusion is enabled. + 2016-06-01 Eric Botcazou <ebotcazou@adacore.com> * tree-vect-loop.c (vect_determine_vectorization_factor): Also take diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index 34fd06a..aaaabb7 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -321,6 +321,7 @@ extern int vfp3_const_double_for_bits (rtx); extern void arm_emit_coreregs_64bit_shift (enum rtx_code, rtx, rtx, rtx, rtx, rtx); +extern bool arm_fusion_enabled_p (tune_params::fuse_ops); extern bool arm_valid_symbolic_address_p (rtx); extern bool arm_validize_comparison (rtx *, rtx *, rtx *); #endif /* RTX_CODE */ diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 16499ce..e924090 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -29858,6 +29858,13 @@ aarch_macro_fusion_pair_p (rtx_insn* prev, rtx_insn* curr) return false; } +/* Return true iff the instruction fusion described by OP is enabled. */ +bool +arm_fusion_enabled_p (tune_params::fuse_ops op) +{ + return current_tune->fusible_ops & op; +} + /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */ static unsigned HOST_WIDE_INT diff --git a/gcc/config/arm/crypto.md b/gcc/config/arm/crypto.md index c6f1727..0f510f0 100644 --- a/gcc/config/arm/crypto.md +++ b/gcc/config/arm/crypto.md @@ -18,14 +18,27 @@ ;; along with GCC; see the file COPYING3. If not see ;; <http://www.gnu.org/licenses/>. + +;; When AES/AESMC fusion is enabled we want the register allocation to +;; look like: +;; AESE Vn, _ +;; AESMC Vn, Vn +;; So prefer to tie operand 1 to operand 0 when fusing. + (define_insn "crypto_<crypto_pattern>" - [(set (match_operand:<crypto_mode> 0 "register_operand" "=w") + [(set (match_operand:<crypto_mode> 0 "register_operand" "=w,w") (unspec:<crypto_mode> [(match_operand:<crypto_mode> 1 - "register_operand" "w")] + "register_operand" "0,w")] CRYPTO_UNARY))] "TARGET_CRYPTO" "<crypto_pattern>.<crypto_size_sfx>\\t%q0, %q1" - [(set_attr "type" "<crypto_type>")] + [(set_attr "type" "<crypto_type>") + (set_attr_alternative "enabled" + [(if_then_else (match_test + "arm_fusion_enabled_p (tune_params::FUSE_AES_AESMC)") + (const_string "yes" ) + (const_string "no")) + (const_string "yes")])] ) (define_insn "crypto_<crypto_pattern>" |