asm-v8.S, [...]: New tests.

	* gcc.target/cris/asm-v8.S, gcc.target/cris/asm-v10.S,
	gcc.target/cris/asm-other.S, gcc.target/cris/inasm-v8.c,
	gcc.target/cris/inasm-v10.c, gcc.target/cris/inasm-other.c:
	New tests.

From-SVN: r188052

7 files changed, 69 insertions, 0 deletions

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 44f71cb..0485dc4 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2012-05-31  Hans-Peter Nilsson  <hp@axis.com>
+
+	* gcc.target/cris/asm-v8.S, gcc.target/cris/asm-v10.S,
+	gcc.target/cris/asm-other.S, gcc.target/cris/inasm-v8.c,
+	gcc.target/cris/inasm-v10.c, gcc.target/cris/inasm-other.c:
+	New tests.
+
 2012-05-30  Jason Merrill  <jason@redhat.com>
 
 	PR c++/53356
diff --git a/gcc/testsuite/gcc.target/cris/asm-other.S b/gcc/testsuite/gcc.target/cris/asm-other.S
new file mode 100644
index 0000000..4fe7ebf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/cris/asm-other.S
@@ -0,0 +1,15 @@
+/* { dg-do assemble } */
+/* { dg-options "-DOTHER_ISA=0 -march=v0" { target crisv32-*-* } } */
+/* { dg-options "-DOTHER_ISA=32 -march=v32" { target cris-*-* } } */
+
+/* Make sure we can assemble for the "other" variant, with the twist
+   that the gcc option -march=v0 isn't valid for the assembler.  */
+        .text
+#if OTHER_ISA == 32
+	addoq 42,$r1,$acr
+#else
+0:
+	move.d [$r2=$r0+42],$r1
+	bwf 0b
+	nop
+#endif
diff --git a/gcc/testsuite/gcc.target/cris/asm-v10.S b/gcc/testsuite/gcc.target/cris/asm-v10.S
new file mode 100644
index 0000000..c85ebe2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/cris/asm-v10.S
@@ -0,0 +1,6 @@
+/* { dg-do assemble } */
+/* { dg-options "-DOTHER_ISA=10 -march=v10" } */
+
+/* Check that -march=v10 is also recognized.  */
+
+#include "asm-other.S"
diff --git a/gcc/testsuite/gcc.target/cris/asm-v8.S b/gcc/testsuite/gcc.target/cris/asm-v8.S
new file mode 100644
index 0000000..3fba318
--- /dev/null
+++ b/gcc/testsuite/gcc.target/cris/asm-v8.S
@@ -0,0 +1,6 @@
+/* { dg-do assemble } */
+/* { dg-options "-DOTHER_ISA=8 -march=v8" } */
+
+/* Check that -march=v8 is also recognized.  */
+
+#include "asm-other.S"
diff --git a/gcc/testsuite/gcc.target/cris/inasm-other.c b/gcc/testsuite/gcc.target/cris/inasm-other.c
new file mode 100644
index 0000000..c1c043f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/cris/inasm-other.c
@@ -0,0 +1,23 @@
+/* { dg-do assemble } */
+/* { dg-options "-DOTHER_ISA=0 -march=v0" { target crisv32-*-* } } */
+/* { dg-options "-DOTHER_ISA=32 -march=v32" { target cris-*-* } } */
+
+/* Make sure we can (generate code and) assemble for the "other"
+   variant, with the twist that the gcc option -march=v0 isn't
+   valid for the assembler.  We don't check that the generated code
+   is for the other variant; other tests cover that already, but they
+   don't *assemble* the result.  We can't trust the prologue and
+   epilogue to contain incompatible insns (they actually deliberately
+   don't, usually and it'd be brittle to tweak the function signature
+   to make it so), so we force some with inline asm.  */
+
+void f(void)
+{
+#if OTHER_ISA == 32
+  asm volatile ("addoq 42,$r11,$acr");
+#else
+  asm volatile ("0: move.d [$r12=$sp+42],$r10\n\t"
+		"bwf 0b\n\t"
+		"nop");
+#endif
+}
diff --git a/gcc/testsuite/gcc.target/cris/inasm-v10.c b/gcc/testsuite/gcc.target/cris/inasm-v10.c
new file mode 100644
index 0000000..75379b3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/cris/inasm-v10.c
@@ -0,0 +1,6 @@
+/* { dg-do assemble } */
+/* { dg-options "-DOTHER_ISA=10 -march=v10" } */
+
+/* Check that -march=v10 is also recognized.  */
+
+#include "inasm-other.c"
diff --git a/gcc/testsuite/gcc.target/cris/inasm-v8.c b/gcc/testsuite/gcc.target/cris/inasm-v8.c
new file mode 100644
index 0000000..b2fb305
--- /dev/null
+++ b/gcc/testsuite/gcc.target/cris/inasm-v8.c
@@ -0,0 +1,6 @@
+/* { dg-do assemble } */
+/* { dg-options "-DOTHER_ISA=8 -march=v8" } */
+
+/* Check that -march=v8 is also recognized.  */
+
+#include "inasm-other.c"