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| author | Andrew Burgess <andrew.burgess@embecosm.com> | 2019-10-16 22:01:25 +0100 |
|---|---|---|
| committer | Jim Wilson <wilson@gcc.gnu.org> | 2019-10-16 14:01:25 -0700 |
| commit | 3599dfbaa22b95ecabd3da9ba68ad4bb4f1124a4 (patch) | |
| tree | 42d8c7d19e6372a7740e691f200a2dc3d658af37 /gcc | |
| parent | 2fcb55d11f4167b966151057c121d0a47914c5c8 (diff) | |
| download | gcc-3599dfbaa22b95ecabd3da9ba68ad4bb4f1124a4.zip gcc-3599dfbaa22b95ecabd3da9ba68ad4bb4f1124a4.tar.gz gcc-3599dfbaa22b95ecabd3da9ba68ad4bb4f1124a4.tar.bz2 | |
RISC-V: Include more registers in SIBCALL_REGS.
This finishes the part 1 of 2 patch submitted by Andrew Burgess on Aug 19.
This adds the argument registers but not t0 (aka x5) to SIBCALL_REGS. It
also adds the missing riscv_regno_to_class change.
Tested with cross riscv32-elf and riscv64-linux toolchain build and check.
There were no regressions. I see about a 0.01% code size reduction for the
C and libstdc++ libraries.
gcc/
* config/riscv/riscv.h (REG_CLASS_CONTENTS): Add argument passing
regs to SIBCALL_REGS.
* config/riscv/riscv.c (riscv_regno_to_class): Change argument
passing regs to SIBCALL_REGS.
Co-Authored-By: Jim Wilson <jimw@sifive.com>
From-SVN: r277082
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/config/riscv/riscv.c | 6 | ||||
| -rw-r--r-- | gcc/config/riscv/riscv.h | 2 |
3 files changed, 12 insertions, 4 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b81945b..5c56e0a 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2019-10-16 Andrew Burgess <andrew.burgess@embecosm.com> + Jim Wilson <jimw@sifive.com> + + * config/riscv/riscv.h (REG_CLASS_CONTENTS): Add argument passing + regs to SIBCALL_REGS. + * config/riscv/riscv.c (riscv_regno_to_class): Change argument + passing regs to SIBCALL_REGS. + 2019-10-16 Martin Sebor <msebor@redhat.com> PR tree-optimization/83821 diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c index b8a8778..77a3ad9 100644 --- a/gcc/config/riscv/riscv.c +++ b/gcc/config/riscv/riscv.c @@ -256,9 +256,9 @@ enum riscv_microarchitecture_type riscv_microarchitecture; const enum reg_class riscv_regno_to_class[FIRST_PSEUDO_REGISTER] = { GR_REGS, GR_REGS, GR_REGS, GR_REGS, GR_REGS, GR_REGS, SIBCALL_REGS, SIBCALL_REGS, - JALR_REGS, JALR_REGS, JALR_REGS, JALR_REGS, - JALR_REGS, JALR_REGS, JALR_REGS, JALR_REGS, - JALR_REGS, JALR_REGS, JALR_REGS, JALR_REGS, + JALR_REGS, JALR_REGS, SIBCALL_REGS, SIBCALL_REGS, + SIBCALL_REGS, SIBCALL_REGS, SIBCALL_REGS, SIBCALL_REGS, + SIBCALL_REGS, SIBCALL_REGS, JALR_REGS, JALR_REGS, JALR_REGS, JALR_REGS, JALR_REGS, JALR_REGS, JALR_REGS, JALR_REGS, JALR_REGS, JALR_REGS, SIBCALL_REGS, SIBCALL_REGS, SIBCALL_REGS, SIBCALL_REGS, diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 5fc9be8..2464946 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -400,7 +400,7 @@ enum reg_class #define REG_CLASS_CONTENTS \ { \ { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ - { 0xf00000c0, 0x00000000, 0x00000000 }, /* SIBCALL_REGS */ \ + { 0xf003fcc0, 0x00000000, 0x00000000 }, /* SIBCALL_REGS */ \ { 0xffffffc0, 0x00000000, 0x00000000 }, /* JALR_REGS */ \ { 0xffffffff, 0x00000000, 0x00000000 }, /* GR_REGS */ \ { 0x00000000, 0xffffffff, 0x00000000 }, /* FP_REGS */ \ |