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| author | Maxim Kuvyrkov <maxim@codesourcery.com> | 2010-07-27 19:42:15 +0000 |
|---|---|---|
| committer | Maxim Kuvyrkov <mkuvyrkov@gcc.gnu.org> | 2010-07-27 19:42:15 +0000 |
| commit | 3393e880c6040bac26ef0b183273877844dd2116 (patch) | |
| tree | dee58e9ff2060acd68d5e7305d5cb5da959a4079 /gcc | |
| parent | eae7938e451f9ec64ca8c1d8781ce4201560b314 (diff) | |
| download | gcc-3393e880c6040bac26ef0b183273877844dd2116.zip gcc-3393e880c6040bac26ef0b183273877844dd2116.tar.gz gcc-3393e880c6040bac26ef0b183273877844dd2116.tar.bz2 | |
re PR target/42495 (redundant memory load)
PR target/42495
PR middle-end/42574
* config/arm/arm.c (thumb1_size_rtx_costs): Add cost for "J" constants.
* config/arm/arm.md (define_split "J", define_split "K"): Make
IRA/reload friendly.
From-SVN: r162594
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/config/arm/arm.c | 4 | ||||
| -rw-r--r-- | gcc/config/arm/arm.md | 19 |
3 files changed, 24 insertions, 7 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index cb9e3b8..c06e7d5 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,13 @@ 2010-07-27 Maxim Kuvyrkov <maxim@codesourcery.com> + PR target/42495 + PR middle-end/42574 + * config/arm/arm.c (thumb1_size_rtx_costs): Add cost for "J" constants. + * config/arm/arm.md (define_split "J", define_split "K"): Make + IRA/reload friendly. + +2010-07-27 Maxim Kuvyrkov <maxim@codesourcery.com> + * gcse.c (insert_insn_end_basic_block): Update signature, remove unused checks. (pre_edge_insert, hoist_code): Update. diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 7b01afb..03c1506 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -7003,6 +7003,10 @@ thumb1_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer) { if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256) return 0; + /* See split "TARGET_THUMB1 && satisfies_constraint_J". */ + if (INTVAL (x) >= -255 && INTVAL (x) <= -1) + return COSTS_N_INSNS (2); + /* See split "TARGET_THUMB1 && satisfies_constraint_K". */ if (thumb_shiftable_const (INTVAL (x))) return COSTS_N_INSNS (2); return COSTS_N_INSNS (3); diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 33b6931..5438b3c 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -5093,17 +5093,21 @@ [(set (match_operand:SI 0 "register_operand" "") (match_operand:SI 1 "const_int_operand" ""))] "TARGET_THUMB1 && satisfies_constraint_J (operands[1])" - [(set (match_dup 0) (match_dup 1)) - (set (match_dup 0) (neg:SI (match_dup 0)))] - "operands[1] = GEN_INT (- INTVAL (operands[1]));" + [(set (match_dup 2) (match_dup 1)) + (set (match_dup 0) (neg:SI (match_dup 2)))] + " + { + operands[1] = GEN_INT (- INTVAL (operands[1])); + operands[2] = can_create_pseudo_p () ? gen_reg_rtx (SImode) : operands[0]; + }" ) (define_split [(set (match_operand:SI 0 "register_operand" "") (match_operand:SI 1 "const_int_operand" ""))] "TARGET_THUMB1 && satisfies_constraint_K (operands[1])" - [(set (match_dup 0) (match_dup 1)) - (set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))] + [(set (match_dup 2) (match_dup 1)) + (set (match_dup 0) (ashift:SI (match_dup 2) (match_dup 3)))] " { unsigned HOST_WIDE_INT val = INTVAL (operands[1]) & 0xffffffffu; @@ -5114,12 +5118,13 @@ if ((val & (mask << i)) == val) break; - /* Shouldn't happen, but we don't want to split if the shift is zero. */ + /* Don't split if the shift is zero. */ if (i == 0) FAIL; operands[1] = GEN_INT (val >> i); - operands[2] = GEN_INT (i); + operands[2] = can_create_pseudo_p () ? gen_reg_rtx (SImode) : operands[0]; + operands[3] = GEN_INT (i); }" ) |