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| author | Richard Sandiford <richard.sandiford@arm.com> | 2019-08-15 08:55:00 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2019-08-15 08:55:00 +0000 |
| commit | 2d2388f82f2e7f2fd1da063192ba98be45f099d2 (patch) | |
| tree | 588378ba2fecfeb6906604a46709aa9c4c2733e7 /gcc | |
| parent | 139df05a29eb71075e42f502978dea4d00a99708 (diff) | |
| download | gcc-2d2388f82f2e7f2fd1da063192ba98be45f099d2.zip gcc-2d2388f82f2e7f2fd1da063192ba98be45f099d2.tar.gz gcc-2d2388f82f2e7f2fd1da063192ba98be45f099d2.tar.bz2 | |
[AArch64] Tweak operand choice for SVE predicate AND
SVE defines an assembly alias:
MOV pa.B, pb/Z, pc.B -> AND pa.B. pb/Z, pc.B, pc.B
Our and<mode>3 pattern was instead using the functionally-equivalent:
AND pa.B. pb/Z, pb.B, pc.B
^^^^
This patch duplicates pc.B instead so that the alias can be seen
in disassembly.
I wondered about using the alias in the pattern instead, but using AND
explicitly seems to fit better with the pattern name and surrounding code.
2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-sve.md (and<PRED_ALL:mode>3): Make the
operand order match the MOV /Z alias.
From-SVN: r274521
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64-sve.md | 4 |
2 files changed, 8 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 873c265..917278e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2019-08-15 Richard Sandiford <richard.sandiford@arm.com> + * config/aarch64/aarch64-sve.md (and<PRED_ALL:mode>3): Make the + operand order match the MOV /Z alias. + +2019-08-15 Richard Sandiford <richard.sandiford@arm.com> + * config/aarch64/aarch64.c (aarch64_output_sve_cnt_immediate): Take the vector pattern as an aarch64_svpattern argument. Update the overloaded caller accordingly. diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index f1f4fa2..ac65e69 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -3317,12 +3317,14 @@ ;; ------------------------------------------------------------------------- ;; Predicate AND. We can reuse one of the inputs as the GP. +;; Doubling the second operand is the preferred implementation +;; of the MOV alias, so we use that instead of %1/z, %1, %2. (define_insn "and<mode>3" [(set (match_operand:PRED_ALL 0 "register_operand" "=Upa") (and:PRED_ALL (match_operand:PRED_ALL 1 "register_operand" "Upa") (match_operand:PRED_ALL 2 "register_operand" "Upa")))] "TARGET_SVE" - "and\t%0.b, %1/z, %1.b, %2.b" + "and\t%0.b, %1/z, %2.b, %2.b" ) ;; Unpredicated predicate EOR and ORR. |