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| author | Renlin Li <renlin.li@arm.com> | 2015-10-02 11:55:04 +0000 |
|---|---|---|
| committer | Renlin Li <renlin@gcc.gnu.org> | 2015-10-02 11:55:04 +0000 |
| commit | 1d3e6ed315efea1a646ce13b57a5c1dc849d6e7e (patch) | |
| tree | 96699282c0bbf11becaa8c85f17d72894f078507 /gcc | |
| parent | bec93d40750bb5dbaa80e96288465e2242337fcf (diff) | |
| download | gcc-1d3e6ed315efea1a646ce13b57a5c1dc849d6e7e.zip gcc-1d3e6ed315efea1a646ce13b57a5c1dc849d6e7e.tar.gz gcc-1d3e6ed315efea1a646ce13b57a5c1dc849d6e7e.tar.bz2 | |
[PATCH][AARCH64][PR66776]Add cmovdi_insn_uxtw pattern.
gcc/
2015-10-02 Renlin Li <renlin.li@arm.com>
PR target/66776
* config/aarch64/aarch64.md (cmovdi_insn_uxtw): New pattern.
gcc/testsuite/
2015-10-02 Renlin Li <renlin.li@arm.com>
PR target/66776
* gcc.target/aarch64/pr66776.c: New.
From-SVN: r228384
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.md | 12 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/pr66776.c | 10 |
4 files changed, 32 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 91c9972..c71a020 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2015-10-02 Renlin Li <renlin.li@arm.com> + + PR target/66776 + * config/aarch64/aarch64.md (cmovdi_insn_uxtw): New pattern. + 2015-10-02 Kyrylo Tkachov <kyrylo.tkachov@arm.com> PR rtl-optimization/67786 diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index c3cd58d..20681cd 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -3010,6 +3010,18 @@ [(set_attr "type" "csel")] ) +(define_insn "*cmovdi_insn_uxtw" + [(set (match_operand:DI 0 "register_operand" "=r") + (if_then_else:DI + (match_operator 1 "aarch64_comparison_operator" + [(match_operand 2 "cc_register" "") (const_int 0)]) + (zero_extend:DI (match_operand:SI 3 "register_operand" "r")) + (zero_extend:DI (match_operand:SI 4 "register_operand" "r"))))] + "" + "csel\\t%w0, %w3, %w4, %m1" + [(set_attr "type" "csel")] +) + (define_insn "*cmov<mode>_insn" [(set (match_operand:GPF 0 "register_operand" "=w") (if_then_else:GPF diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 169c0c4..87bcd8b 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2015-10-02 Renlin Li <renlin.li@arm.com> + + PR target/66776 + * gcc.target/aarch64/pr66776.c: New. + 2015-10-02 Eric Botcazou <ebotcazou@adacore.com> * gnat.dg/warn13.adb: New test. diff --git a/gcc/testsuite/gcc.target/aarch64/pr66776.c b/gcc/testsuite/gcc.target/aarch64/pr66776.c new file mode 100644 index 0000000..a5c83b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr66776.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 --save-temps" } */ + +unsigned long long +foo (unsigned int a, unsigned int b, unsigned int c) +{ + return a ? b : c; +} + +/* { dg-final { scan-assembler-not "uxtw" } } */ |