aboutsummaryrefslogtreecommitdiff
path: root/gcc
diff options
context:
space:
mode:
authorJoseph Myers <joseph@codesourcery.com>2006-11-16 13:36:23 +0000
committerJoseph Myers <jsm28@gcc.gnu.org>2006-11-16 13:36:23 +0000
commit198bc7873d1ec1ead4e8db307e0e4cc1fca81370 (patch)
tree0c487dcd573cfe3cbfc5f3f3e61c7a2acd327cf0 /gcc
parent9f1dce5609ca54d2caa87d0ecfece64a7bb58c81 (diff)
downloadgcc-198bc7873d1ec1ead4e8db307e0e4cc1fca81370.zip
gcc-198bc7873d1ec1ead4e8db307e0e4cc1fca81370.tar.gz
gcc-198bc7873d1ec1ead4e8db307e0e4cc1fca81370.tar.bz2
spe.md (frob_di_df_2): Handle non-offsettable memory operand.
* config/rs6000/spe.md (frob_di_df_2): Handle non-offsettable memory operand. From-SVN: r118889
Diffstat (limited to 'gcc')
-rw-r--r--gcc/ChangeLog5
-rw-r--r--gcc/config/rs6000/spe.md5
2 files changed, 10 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index c5ae49a..fed1fb5 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2006-11-16 Joseph Myers <joseph@codesourcery.com>
+
+ * config/rs6000/spe.md (frob_di_df_2): Handle non-offsettable
+ memory operand.
+
2006-11-16 Richard Earnshaw <rearnsha@arm.com>
* arm.md (abssi2): Allow Thumb as well. Use an SImode scratch for
diff --git a/gcc/config/rs6000/spe.md b/gcc/config/rs6000/spe.md
index 1ac1a84..f2410dd 100644
--- a/gcc/config/rs6000/spe.md
+++ b/gcc/config/rs6000/spe.md
@@ -2223,6 +2223,11 @@
case 0:
return \"evmergehi %0,%1,%1\;mr %L0,%1\";
case 1:
+ /* If the address is not offsettable we need to load the whole
+ doubleword into a 64-bit register and then copy the high word
+ to form the correct output layout. */
+ if (!offsettable_nonstrict_memref_p (operands[1]))
+ return \"evldd%X1 %L0,%y1\;evmergehi %0,%L0,%L0\";
/* If the low-address word is used in the address, we must load
it last. Otherwise, load it first. Note that we cannot have
auto-increment in that case since the address register is