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| author | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2019-02-20 14:11:43 +0000 |
|---|---|---|
| committer | Andre Vieira <avieira@gcc.gnu.org> | 2019-02-20 14:11:43 +0000 |
| commit | 145d4e1a4e15b16a41ff148c61d8b4230778edb8 (patch) | |
| tree | 15e857c5548cc7cba473893bc803632ca9107f4e /gcc | |
| parent | c9ea5b639bac7750bb1a3ba03a1c6c72e1abe4ad (diff) | |
| download | gcc-145d4e1a4e15b16a41ff148c61d8b4230778edb8.zip gcc-145d4e1a4e15b16a41ff148c61d8b4230778edb8.tar.gz gcc-145d4e1a4e15b16a41ff148c61d8b4230778edb8.tar.bz2 | |
[GCC] PR target/86487: fix the way 'uses_hard_regs_p' handles paradoxical
subregs
gcc/ChangeLog:
2019-02-20 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR target/86487
* lra-constraints.c(uses_hard_regs_p): Fix handling of
paradoxical SUBREGS.
gcc/testsuite/ChangeLog:
2019-02-20 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR target/86487
* gcc.target/arm/pr86487.c: New.
From-SVN: r269039
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/lra-constraints.c | 16 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/arm/pr86487.c | 10 |
4 files changed, 34 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b18b23c..b544e08 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2019-02-20 Andre Vieira <andre.simoesdiasvieira@arm.com> + + PR target/86487 + * lra-constraints.c(uses_hard_regs_p): Fix handling of + paradoxical SUBREGS. + 2019-02-20 Li Jia He <helijia@linux.ibm.com> PR target/88100 diff --git a/gcc/lra-constraints.c b/gcc/lra-constraints.c index 17ea2c5..629dc5d 100644 --- a/gcc/lra-constraints.c +++ b/gcc/lra-constraints.c @@ -1770,14 +1770,24 @@ uses_hard_regs_p (rtx x, HARD_REG_SET set) return false; code = GET_CODE (x); mode = GET_MODE (x); + if (code == SUBREG) { + /* For all SUBREGs we want to check whether the full multi-register + overlaps the set. For normal SUBREGs this means 'get_hard_regno' of + the inner register, for paradoxical SUBREGs this means the + 'get_hard_regno' of the full SUBREG and for complete SUBREGs either is + fine. Use the wider mode for all cases. */ + rtx subreg = SUBREG_REG (x); mode = wider_subreg_mode (x); - x = SUBREG_REG (x); - code = GET_CODE (x); + if (mode == GET_MODE (subreg)) + { + x = subreg; + code = GET_CODE (x); + } } - if (REG_P (x)) + if (REG_P (x) || SUBREG_P (x)) { x_hard_regno = get_hard_regno (x, true); return (x_hard_regno >= 0 diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index cd45bc5..3b415cd 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2019-02-20 Andre Vieira <andre.simoesdiasvieira@arm.com> + + PR target/86487 + * gcc.target/arm/pr86487.c: New. + 2019-02-20 Paolo Carlini <paolo.carlini@oracle.com> PR c++/84536 diff --git a/gcc/testsuite/gcc.target/arm/pr86487.c b/gcc/testsuite/gcc.target/arm/pr86487.c new file mode 100644 index 0000000..1c1db78 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr86487.c @@ -0,0 +1,10 @@ +/* { dg-skip-if "" { *-*-* } { "-march=armv[0-6]*" "-mthumb" } { "" } } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O1 -mbig-endian" } */ +/* { dg-add-options arm_neon } */ +int a, b, c, d; +long long fn1(long long p2) { return p2 == 0 ? -1 : -1 % p2; } +void fn2(long long p1, short p2, long p3) { + b = fn1((d || 6) & a); + c = b | p3; +} |