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| author | H.J. Lu <hongjiu.lu@intel.com> | 2019-09-18 19:49:19 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl@gcc.gnu.org> | 2019-09-18 12:49:19 -0700 |
| commit | 101a0841b6fad201172e90f716d6c1866d7b0a36 (patch) | |
| tree | 8bf69732553f5ab877eee2dbbdf83545ef978e34 /gcc | |
| parent | 22a8ab772c37dc6250f2b22afe1e91b55fda41f5 (diff) | |
| download | gcc-101a0841b6fad201172e90f716d6c1866d7b0a36.zip gcc-101a0841b6fad201172e90f716d6c1866d7b0a36.tar.gz gcc-101a0841b6fad201172e90f716d6c1866d7b0a36.tar.bz2 | |
i386: Increase Skylake SImode pseudo register store cost
On Skylake, SImode store cost isn't less than half cost of 128-bit vector
store. This patch increases Skylake SImode pseudo register store cost to
make it the same as QImode and HImode.
gcc/
PR target/91446
* config/i386/x86-tune-costs.h (skylake_cost): Increase SImode
pseudo register store cost from 3 to 6 to make it the same as
QImode and HImode.
gcc/testsuite/
PR target/91446
* gcc.target/i386/pr91446.c: New test.
From-SVN: r275905
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/i386/x86-tune-costs.h | 2 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/pr91446.c | 24 |
4 files changed, 37 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6be55cd..d74b19f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2019-09-18 H.J. Lu <hongjiu.lu@intel.com> + + PR target/91446 + * config/i386/x86-tune-costs.h (skylake_cost): Increase SImode + pseudo register store cost from 3 to 6 to make it the same as + QImode and HImode. + 2019-09-18 Wilco Dijkstra <wdijkstr@arm.com> * config/arm/arm.md (maddsidi4): Remove expander. diff --git a/gcc/config/i386/x86-tune-costs.h b/gcc/config/i386/x86-tune-costs.h index 00edece..42c9c25 100644 --- a/gcc/config/i386/x86-tune-costs.h +++ b/gcc/config/i386/x86-tune-costs.h @@ -1638,7 +1638,7 @@ struct processor_costs skylake_cost = { {4, 4, 4}, /* cost of loading integer registers in QImode, HImode and SImode. Relative to reg-reg move (2). */ - {6, 6, 3}, /* cost of storing integer registers */ + {6, 6, 6}, /* cost of storing integer registers */ {6, 6, 6, 10, 20}, /* cost of loading SSE register in 32bit, 64bit, 128bit, 256bit and 512bit */ {8, 8, 8, 12, 24}, /* cost of storing SSE register diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index dc84ed9..8ea581d 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2019-09-18 H.J. Lu <hongjiu.lu@intel.com> + + PR target/91446 + * gcc.target/i386/pr91446.c: New test. + 2019-09-18 Eric Botcazou <ebotcazou@adacore.com> * gnat.dg/warn31.adb, gnat.dg/warn31.ads: New testcase. diff --git a/gcc/testsuite/gcc.target/i386/pr91446.c b/gcc/testsuite/gcc.target/i386/pr91446.c new file mode 100644 index 0000000..f7c4bea --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr91446.c @@ -0,0 +1,24 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -march=skylake -ftree-slp-vectorize -mtune-ctrl=^sse_typeless_stores" } */ + +typedef struct +{ + unsigned long long width, height; + long long x, y; +} info; + +extern void bar (info *); + +void +foo (unsigned long long width, unsigned long long height, + long long x, long long y) +{ + info t; + t.width = width; + t.height = height; + t.x = x; + t.y = y; + bar (&t); +} + +/* { dg-final { scan-assembler-times "vmovdqa\[^\n\r\]*xmm\[0-9\]" 2 } } */ |