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| author | Renlin Li <renlin.li@arm.com> | 2015-10-02 12:52:36 +0000 |
|---|---|---|
| committer | Renlin Li <renlin@gcc.gnu.org> | 2015-10-02 12:52:36 +0000 |
| commit | 0f6ca79c15711e28ea7a6330fc9ac017077fbaad (patch) | |
| tree | f39108f5da865608cdb1acb95e1ddc76e5469e44 /gcc | |
| parent | b03e67ad92a848598de050da268ccbf7832a2197 (diff) | |
| download | gcc-0f6ca79c15711e28ea7a6330fc9ac017077fbaad.zip gcc-0f6ca79c15711e28ea7a6330fc9ac017077fbaad.tar.gz gcc-0f6ca79c15711e28ea7a6330fc9ac017077fbaad.tar.bz2 | |
[PATCH][AARCH64]Add csneg3_uxtw_insn pattern
gcc/
2015-10-02 Renlin Li <renlin.li@arm.com>
* config/aarch64/aarch64.md (csneg3_uxtw_insn): New pattern.
gcc/testsuite/
2015-10-02 Renlin Li <renlin.li@arm.com>
* gcc.target/aarch64/csneg-1.c: Update test.
From-SVN: r228387
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.md | 12 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/csneg-1.c | 12 |
4 files changed, 32 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a84b8a9..57a5a43 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -5,6 +5,10 @@ 2015-10-02 Renlin Li <renlin.li@arm.com> + * config/aarch64/aarch64.md (csneg3_insn_uxtw): New pattern. + +2015-10-02 Renlin Li <renlin.li@arm.com> + PR target/66776 * config/aarch64/aarch64.md (cmovdi_insn_uxtw): New pattern. diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 20681cd..74522f8 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -3144,6 +3144,18 @@ [(set_attr "type" "csel")] ) +(define_insn "csneg3_uxtw_insn" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI + (if_then_else:SI + (match_operand 1 "aarch64_comparison_operation" "") + (neg:SI (match_operand:SI 2 "register_operand" "r")) + (match_operand:SI 3 "aarch64_reg_or_zero" "rZ"))))] + "" + "csneg\\t%w0, %w3, %w2, %M1" + [(set_attr "type" "csel")] +) + (define_insn "csneg3<mode>_insn" [(set (match_operand:GPI 0 "register_operand" "=r") (if_then_else:GPI diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 87bcd8b..c95cda9 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,9 @@ 2015-10-02 Renlin Li <renlin.li@arm.com> + * gcc.target/aarch64/csneg-1.c: Update. + +2015-10-02 Renlin Li <renlin.li@arm.com> + PR target/66776 * gcc.target/aarch64/pr66776.c: New. diff --git a/gcc/testsuite/gcc.target/aarch64/csneg-1.c b/gcc/testsuite/gcc.target/aarch64/csneg-1.c index 29d4e4e..4860d64 100644 --- a/gcc/testsuite/gcc.target/aarch64/csneg-1.c +++ b/gcc/testsuite/gcc.target/aarch64/csneg-1.c @@ -56,3 +56,15 @@ int test_csneg_cmp(int x) x = -x; return x; } + +unsigned long long +test_csneg_uxtw (unsigned int a, + unsigned int b, + unsigned int c) +{ + /* { dg-final { scan-assembler "csneg\tw\[0-9\]*.*ne" } } */ + /* { dg-final { scan-assembler-not "uxtw\tw\[0-9\]*.*" } } */ + unsigned int val; + val = a ? b: -c; + return val; +} |