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| author | Bin Cheng <amker@gcc.gnu.org> | 2017-07-25 08:31:22 +0000 |
|---|---|---|
| committer | Bin Cheng <amker@gcc.gnu.org> | 2017-07-25 08:31:22 +0000 |
| commit | 0e82a9b9422447fe9730831a5072655e0f5780f7 (patch) | |
| tree | c3f330e9c0fa90138c5a86b8865d315e0d6919cf /gcc | |
| parent | 198104af576c095b74ab456d95f6b4080e408a37 (diff) | |
| download | gcc-0e82a9b9422447fe9730831a5072655e0f5780f7.zip gcc-0e82a9b9422447fe9730831a5072655e0f5780f7.tar.gz gcc-0e82a9b9422447fe9730831a5072655e0f5780f7.tar.bz2 | |
re PR target/81414 (ICE in fma steering on AArch64/cortex-a57)
PR target/81414
* config/aarch64/cortex-a57-fma-steering.c (analyze): Skip fmul/fmac
instructions if no du chain is found.
gcc/testsuite
* gcc.target/aarch64/pr81414.C: New.
From-SVN: r250496
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/aarch64/cortex-a57-fma-steering.c | 15 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/pr81414.C | 9 |
4 files changed, 31 insertions, 4 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3ff7b90..24d9088 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2017-07-25 Bin Cheng <bin.cheng@arm.com> + + PR target/81414 + * config/aarch64/cortex-a57-fma-steering.c (analyze): Skip fmul/fmac + instructions if no du chain is found. + 2017-07-25 Georg-Johann Lay <avr@gjlay.de> * config/avr/avr-log.c (avr_log_vadump) ['T']: Print NULL-TREE. diff --git a/gcc/config/aarch64/cortex-a57-fma-steering.c b/gcc/config/aarch64/cortex-a57-fma-steering.c index 6d90acd..fa8c56a 100644 --- a/gcc/config/aarch64/cortex-a57-fma-steering.c +++ b/gcc/config/aarch64/cortex-a57-fma-steering.c @@ -973,10 +973,17 @@ func_fma_steering::analyze () break; } - /* We didn't find a chain with a def for this instruction. */ - gcc_assert (i < dest_op_info->n_chains); - - this->analyze_fma_fmul_insn (forest, chain, head); + /* Due to implementation of regrename, dest register can slip away + from regrename's analysis. As a result, there is no chain for + the destination register of insn. We simply skip the insn even + it is a fmul/fmac instruction. This can happen when the dest + register is also a source register of insn and one of the below + conditions is satisfied: + 1) the source reg is setup in larger mode than this insn; + 2) the source reg is uninitialized; + 3) the source reg is passed in as parameter. */ + if (i < dest_op_info->n_chains) + this->analyze_fma_fmul_insn (forest, chain, head); } } free (bb_dfs_preorder); diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 82119f1..aef24ec 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2017-07-25 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + PR target/81414 + * gcc.target/aarch64/pr81414.C: New. + 2017-07-25 Richard Biener <rguenther@suse.de> PR middle-end/81505 diff --git a/gcc/testsuite/gcc.target/aarch64/pr81414.C b/gcc/testsuite/gcc.target/aarch64/pr81414.C new file mode 100644 index 0000000..53dfc7c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr81414.C @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mcpu=cortex-a57" } */ + +typedef __Float32x2_t float32x2_t; +float32x2_t +foo1 (float32x2_t __a, float32x2_t __b, float32x2_t __c) { + return __b * __c + __a; +} + |