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| author | Claudiu Zissulescu <claziss@synopsys.com> | 2017-03-13 13:56:22 +0100 |
|---|---|---|
| committer | Claudiu Zissulescu <claziss@gcc.gnu.org> | 2017-03-13 13:56:22 +0100 |
| commit | 0e5172ebf287a857364a0e8be216e3231258bc49 (patch) | |
| tree | ab1dd02665910d28be40d85cade651a67290cb2b /gcc | |
| parent | 8c56cc5a88342b2c327bdcee9245e4afd86a8862 (diff) | |
| download | gcc-0e5172ebf287a857364a0e8be216e3231258bc49.zip gcc-0e5172ebf287a857364a0e8be216e3231258bc49.tar.gz gcc-0e5172ebf287a857364a0e8be216e3231258bc49.tar.bz2 | |
[ARC] Code size modifications.
gcc/
2017-03-13 Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc.c (arc_init): Use multiplier whenever we have it.
(arc_conditional_register_usage): Use a different allocation order
when optimizing for size.
* common/config/arc/arc-common.c (arc_option_optimization_table):
Section anchors default on when optimizing for size.
From-SVN: r246091
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/common/config/arc/arc-common.c | 1 | ||||
| -rw-r--r-- | gcc/config/arc/arc.c | 56 |
3 files changed, 51 insertions, 14 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1c160a5..b00a0cd 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,13 @@ 2017-03-13 Claudiu Zissulescu <claziss@synopsys.com> + * config/arc/arc.c (arc_init): Use multiplier whenever we have it. + (arc_conditional_register_usage): Use a different allocation order + when optimizing for size. + * common/config/arc/arc-common.c (arc_option_optimization_table): + Section anchors default on when optimizing for size. + +2017-03-13 Claudiu Zissulescu <claziss@synopsys.com> + * config/arc/arc.md (*tst_bitfield_tst): Fix pattern. 2017-03-13 Claudiu Zissulescu <claziss@synopsys.com> diff --git a/gcc/common/config/arc/arc-common.c b/gcc/common/config/arc/arc-common.c index 88bfec6..82e0dd3 100644 --- a/gcc/common/config/arc/arc-common.c +++ b/gcc/common/config/arc/arc-common.c @@ -46,6 +46,7 @@ arc_option_init_struct (struct gcc_options *opts) #define OPT_LEVELS_3_PLUS_SPEED_ONLY OPT_LEVELS_3_PLUS static const struct default_options arc_option_optimization_table[] = { + { OPT_LEVELS_SIZE, OPT_fsection_anchors, NULL, 1 }, { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 }, { OPT_LEVELS_ALL, OPT_mRcq, NULL, 1 }, { OPT_LEVELS_ALL, OPT_mRcw, NULL, 1 }, diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c index 5826c40..1116b2d 100644 --- a/gcc/config/arc/arc.c +++ b/gcc/config/arc/arc.c @@ -676,6 +676,12 @@ make_pass_arc_predicate_delay_insns (gcc::context *ctxt) static void arc_init (void) { + if (TARGET_V2) + { + /* I have the multiplier, then use it*/ + if (TARGET_MPYW || TARGET_MULTI) + arc_multcost = COSTS_N_INSNS (1); + } /* Note: arc_multcost is only used in rtx_cost if speed is true. */ if (arc_multcost < 0) switch (arc_tune) @@ -1374,20 +1380,42 @@ arc_conditional_register_usage (void) } if (TARGET_Q_CLASS) { - reg_alloc_order[2] = 12; - reg_alloc_order[3] = 13; - reg_alloc_order[4] = 14; - reg_alloc_order[5] = 15; - reg_alloc_order[6] = 1; - reg_alloc_order[7] = 0; - reg_alloc_order[8] = 4; - reg_alloc_order[9] = 5; - reg_alloc_order[10] = 6; - reg_alloc_order[11] = 7; - reg_alloc_order[12] = 8; - reg_alloc_order[13] = 9; - reg_alloc_order[14] = 10; - reg_alloc_order[15] = 11; + if (optimize_size) + { + reg_alloc_order[0] = 0; + reg_alloc_order[1] = 1; + reg_alloc_order[2] = 2; + reg_alloc_order[3] = 3; + reg_alloc_order[4] = 12; + reg_alloc_order[5] = 13; + reg_alloc_order[6] = 14; + reg_alloc_order[7] = 15; + reg_alloc_order[8] = 4; + reg_alloc_order[9] = 5; + reg_alloc_order[10] = 6; + reg_alloc_order[11] = 7; + reg_alloc_order[12] = 8; + reg_alloc_order[13] = 9; + reg_alloc_order[14] = 10; + reg_alloc_order[15] = 11; + } + else + { + reg_alloc_order[2] = 12; + reg_alloc_order[3] = 13; + reg_alloc_order[4] = 14; + reg_alloc_order[5] = 15; + reg_alloc_order[6] = 1; + reg_alloc_order[7] = 0; + reg_alloc_order[8] = 4; + reg_alloc_order[9] = 5; + reg_alloc_order[10] = 6; + reg_alloc_order[11] = 7; + reg_alloc_order[12] = 8; + reg_alloc_order[13] = 9; + reg_alloc_order[14] = 10; + reg_alloc_order[15] = 11; + } } if (TARGET_SIMD_SET) { |