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| author | Kugan Vivekanandarajah <kuganv@linaro.org> | 2019-03-30 04:24:22 +0000 |
|---|---|---|
| committer | Kugan Vivekanandarajah <kugan@gcc.gnu.org> | 2019-03-30 04:24:22 +0000 |
| commit | 09062aa45c273ef70653be0f2541af1923a37bac (patch) | |
| tree | cdb8d4254ce59d5df435535aa8c8d362e079b98b /gcc | |
| parent | 593f8d6466aeb25067932d80cf2b655524cf958e (diff) | |
| download | gcc-09062aa45c273ef70653be0f2541af1923a37bac.zip gcc-09062aa45c273ef70653be0f2541af1923a37bac.tar.gz gcc-09062aa45c273ef70653be0f2541af1923a37bac.tar.bz2 | |
re PR rtl-optimization/89862 (LTO bootstrap fails for ARM)
2019-03-29 Kugan Vivekanandarajah <kuganv@linaro.org>
Eric Botcazou <ebotcazou@adacore.com>
PR rtl-optimization/89862
* rtl.h (word_register_operation_p): Exclude CONST_INT from operations
that operates on the full registers for WORD_REGISTER_OPERATIONS
architectures.
Co-Authored-By: Eric Botcazou <ebotcazou@adacore.com>
From-SVN: r270030
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/rtl.h | 1 |
2 files changed, 9 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a9b1ee7..1367851 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2019-03-29 Kugan Vivekanandarajah <kuganv@linaro.org> + Eric Botcazou <ebotcazou@adacore.com> + + PR rtl-optimization/89862 + * rtl.h (word_register_operation_p): Exclude CONST_INT from operations + that operates on the full registers for WORD_REGISTER_OPERATIONS + architectures. + 2019-03-29 Jim Wilson <jimw@sifive.com> * common/config/riscv/riscv-common.c (riscv_parse_arch_string): @@ -4400,6 +4400,7 @@ word_register_operation_p (const_rtx x) { switch (GET_CODE (x)) { + case CONST_INT: case ROTATE: case ROTATERT: case SIGN_EXTRACT: |