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| author | Stan Shebs <shebs@apple.com> | 2001-11-17 21:17:53 +0000 |
|---|---|---|
| committer | Stan Shebs <shebs@gcc.gnu.org> | 2001-11-17 21:17:53 +0000 |
| commit | 089a05b8d7a14016a8bb36c94170a1c0e72872da (patch) | |
| tree | a46d5a672601b078108980c013ee485d27bfed02 /gcc | |
| parent | 572202a718776c8d1a7d7f467652a2faff940c6c (diff) | |
| download | gcc-089a05b8d7a14016a8bb36c94170a1c0e72872da.zip gcc-089a05b8d7a14016a8bb36c94170a1c0e72872da.tar.gz gcc-089a05b8d7a14016a8bb36c94170a1c0e72872da.tar.bz2 | |
rs6000.h (REG_CLASS_CONTENTS): Fix the AltiVec-related bitfields.
* config/rs6000/rs6000.h (REG_CLASS_CONTENTS): Fix the
AltiVec-related bitfields.
From-SVN: r47127
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.h | 12 |
2 files changed, 11 insertions, 6 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 9166e26..bdf40d7 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2001-11-17 Stan Shebs <shebs@apple.com> + + * config/rs6000/rs6000.h (REG_CLASS_CONTENTS): Fix the + AltiVec-related bitfields. + Sat Nov 17 12:06:31 2001 Richard Kenner <kenner@vlsi1.ultra.nyu.edu> * except.c (enum eh_region_type): Add ERT_UNKNOWN. diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index ab0af2e..238cedc 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -1055,8 +1055,8 @@ enum reg_class { 0xfffffffe, 0x00000000, 0x00000008, 0x00000000 }, /* BASE_REGS */ \ { 0xffffffff, 0x00000000, 0x00000008, 0x00000000 }, /* GENERAL_REGS */ \ { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \ - { 0x00000000, 0x00000000, 0xffffe000, 0x0001ffff }, /* ALTIVEC_REGS */ \ - { 0x00000000, 0x00000000, 0x00000000, 0x00020000 }, /* VRSAVE_REGS */ \ + { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */ \ + { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */ \ { 0xffffffff, 0xffffffff, 0x00000008, 0x00000000 }, /* NON_SPECIAL_REGS */ \ { 0x00000000, 0x00000000, 0x00000001, 0x00000000 }, /* MQ_REGS */ \ { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \ @@ -1066,9 +1066,9 @@ enum reg_class { 0xffffffff, 0x00000000, 0x0000000f, 0x00000000 }, /* SPEC_OR_GEN_REGS */ \ { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \ { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \ - { 0xffffffff, 0x00000000, 0x0000ffff, 0x00000000 }, /* NON_FLOAT_REGS */ \ - { 0x00000000, 0x00000000, 0x00010000, 0x00000000 }, /* XER_REGS */ \ - { 0xffffffff, 0xffffffff, 0xffffffff, 0x0003ffff } /* ALL_REGS */ \ + { 0xffffffff, 0x00000000, 0x0000efff, 0x00000000 }, /* NON_FLOAT_REGS */ \ + { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* XER_REGS */ \ + { 0xffffffff, 0xffffffff, 0xffffffff, 0x00003fff } /* ALL_REGS */ \ } /* The same information, inverted: @@ -2069,7 +2069,7 @@ do { \ /* Define this macro if the register defined by `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define - this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */ + this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */ /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */ |