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| author | Jim Wilson <wilson@cygnus.com> | 1997-10-28 19:56:50 +0000 |
|---|---|---|
| committer | Jim Wilson <wilson@gcc.gnu.org> | 1997-10-28 11:56:50 -0800 |
| commit | 0841747819935a6f6def03b9c5f335e5755b7dc2 (patch) | |
| tree | c2dab20bc22bb2000243a63c2579bed3ce6d18e6 /gcc | |
| parent | 750e83485a2a2e2a6b09368000961827d0f7b8a8 (diff) | |
| download | gcc-0841747819935a6f6def03b9c5f335e5755b7dc2.zip gcc-0841747819935a6f6def03b9c5f335e5755b7dc2.tar.gz gcc-0841747819935a6f6def03b9c5f335e5755b7dc2.tar.bz2 | |
Fix coldfire/btst problems.
* m68k.md (btst patterns): Add 5200 support.
From-SVN: r16217
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/config/m68k/m68k.md | 44 |
2 files changed, 45 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0b3f40f..0582060 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,7 @@ +Tue Oct 28 11:53:14 1997 Jim Wilson <wilson@cygnus.com> + + * m68k.md (btst patterns): Add 5200 support. + Tue Oct 28 11:58:40 1997 Toon Moene <toon@moene.indiv.nluug.nl> * fold-const.c (fold): For ((a * C1) / C3) or (((a * C1) + C2) / C3) diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md index 2413c64..3a54b6d 100644 --- a/gcc/config/m68k/m68k.md +++ b/gcc/config/m68k/m68k.md @@ -749,12 +749,27 @@ ;; Recognizers for btst instructions. +;; Coldfire/5200 only allows "<Q>" type addresses when the bit position is +;; specified as a constant, so we must disable all patterns that may extract +;; from a MEM at a constant bit position if we can't use this as a constraint. + (define_insn "" [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o") (const_int 1) (minus:SI (const_int 7) (match_operand:SI 1 "general_operand" "di"))))] - "" + "!TARGET_5200" + "* { return output_btst (operands, operands[1], operands[0], insn, 7); }") + +;; This is the same as the above pattern except for the constraints. The 'i' +;; has been deleted. + +(define_insn "" + [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o") + (const_int 1) + (minus:SI (const_int 7) + (match_operand:SI 1 "general_operand" "d"))))] + "TARGET_5200" "* { return output_btst (operands, operands[1], operands[0], insn, 7); }") (define_insn "" @@ -795,7 +810,7 @@ [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m") (const_int 1) (match_operand:SI 1 "const_int_operand" "n")))] - "(unsigned) INTVAL (operands[1]) < 8" + "(unsigned) INTVAL (operands[1]) < 8 && !TARGET_5200" "* { operands[1] = gen_rtx (CONST_INT, VOIDmode, 7 - INTVAL (operands[1])); @@ -806,7 +821,30 @@ [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "do") (const_int 1) (match_operand:SI 1 "const_int_operand" "n")))] - "" + "!TARGET_5200" + "* +{ + if (GET_CODE (operands[0]) == MEM) + { + operands[0] = adj_offsettable_operand (operands[0], + INTVAL (operands[1]) / 8); + operands[1] = gen_rtx (CONST_INT, VOIDmode, + 7 - INTVAL (operands[1]) % 8); + return output_btst (operands, operands[1], operands[0], insn, 7); + } + operands[1] = gen_rtx (CONST_INT, VOIDmode, + 31 - INTVAL (operands[1])); + return output_btst (operands, operands[1], operands[0], insn, 31); +}") + +;; This is the same as the above pattern except for the constraints. +;; The 'o' has been replaced with 'Q'. + +(define_insn "" + [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "dQ") + (const_int 1) + (match_operand:SI 1 "const_int_operand" "n")))] + "TARGET_5200" "* { if (GET_CODE (operands[0]) == MEM) |