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| author | Oleg Endo <olegendo@gcc.gnu.org> | 2012-08-21 23:34:54 +0000 |
|---|---|---|
| committer | Oleg Endo <olegendo@gcc.gnu.org> | 2012-08-21 23:34:54 +0000 |
| commit | 082ea1dcd5541bcbda512a1ba758997e54e3ae26 (patch) | |
| tree | 08d8b1ddf0f7cf20cea6df24ddf79766ffaddf13 /gcc | |
| parent | 1aee89910ada0e1d9ab68263e441341038bf9cad (diff) | |
| download | gcc-082ea1dcd5541bcbda512a1ba758997e54e3ae26.zip gcc-082ea1dcd5541bcbda512a1ba758997e54e3ae26.tar.gz gcc-082ea1dcd5541bcbda512a1ba758997e54e3ae26.tar.bz2 | |
re PR target/39423 ([SH] performance regression: lost mov @(disp,Rn))
PR target/39423
* config/sh/sh.md (*movhi_index_disp): Add support for SH2A movu.w insn.
PR target/39423
* gcc.target/sh/pr39423-2.c: New.
From-SVN: r190579
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/sh/sh.md | 33 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/sh/pr39423-2.c | 14 |
4 files changed, 52 insertions, 5 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 7400fe8..30d2335 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2012-08-21 Oleg Endo <olegendo@gcc.gnu.org> + + PR target/39423 + * config/sh/sh.md (*movhi_index_disp): Add support for SH2A movu.w insn. + 2012-08-21 H.J. Lu <hongjiu.lu@intel.com> PR middle-end/54332 diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md index d38fd20..bc2a6c1 100644 --- a/gcc/config/sh/sh.md +++ b/gcc/config/sh/sh.md @@ -5793,12 +5793,35 @@ label: (clobber (reg:SI T_REG))] "TARGET_SH1" "#" - "&& 1" - [(parallel [(set (match_dup 0) (sign_extend:SI (match_dup 1))) - (clobber (reg:SI T_REG))]) - (set (match_dup 0) (zero_extend:SI (match_dup 2)))] + "&& can_create_pseudo_p ()" + [(const_int 0)] { - operands[2] = gen_lowpart (HImode, operands[0]); + rtx mem = operands[1]; + rtx plus0_rtx = XEXP (mem, 0); + rtx plus1_rtx = XEXP (plus0_rtx, 0); + rtx mult_rtx = XEXP (plus1_rtx, 0); + + rtx op_1 = XEXP (mult_rtx, 0); + rtx op_2 = GEN_INT (exact_log2 (INTVAL (XEXP (mult_rtx, 1)))); + rtx op_3 = XEXP (plus1_rtx, 1); + rtx op_4 = XEXP (plus0_rtx, 1); + rtx op_5 = gen_reg_rtx (SImode); + rtx op_6 = gen_reg_rtx (SImode); + rtx op_7 = replace_equiv_address (mem, gen_rtx_PLUS (SImode, op_6, op_4)); + + emit_insn (gen_ashlsi3 (op_5, op_1, op_2)); + emit_insn (gen_addsi3 (op_6, op_5, op_3)); + + /* On SH2A the movu.w insn can be used for zero extending loads. */ + if (TARGET_SH2A) + emit_insn (gen_zero_extendhisi2 (operands[0], op_7)); + else + { + emit_insn (gen_extendhisi2 (operands[0], op_7)); + emit_insn (gen_zero_extendhisi2 (operands[0], + gen_lowpart (HImode, operands[0]))); + } + DONE; }) (define_insn_and_split "*movsi_index_disp" diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 9bdd4f8..6724380 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2012-08-21 Oleg Endo <olegendo@gcc.gnu.org> + + PR target/39423 + * gcc.target/sh/pr39423-2.c: New. + 2012-08-21 Marc Glisse <marc.glisse@inria.fr> * gcc.dg/tree-ssa/forwprop-19.c: New testcase. diff --git a/gcc/testsuite/gcc.target/sh/pr39423-2.c b/gcc/testsuite/gcc.target/sh/pr39423-2.c new file mode 100644 index 0000000..8e71505 --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/pr39423-2.c @@ -0,0 +1,14 @@ +/* Check that displacement addressing is used for indexed addresses with a + small offset, instead of re-calculating the index and that the movu.w + instruction is used on SH2A. */ +/* { dg-do compile { target "sh*-*-*" } } */ +/* { dg-options "-O2" } */ +/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" } } */ +/* { dg-final { scan-assembler-not "add\t#1" } } */ +/* { dg-final { scan-assembler "movu.w" } } */ + +int +test_00 (unsigned short tab[], int index) +{ + return tab[index + 1]; +} |