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| author | H.J. Lu <hongjiu.lu@intel.com> | 2019-05-15 15:06:28 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl@gcc.gnu.org> | 2019-05-15 08:06:28 -0700 |
| commit | 08266db93f51f2bf4fe3a211c2f9f4bf1875f725 (patch) | |
| tree | 9a9380495ed49dcb51611f7221c54ab6f4785ac0 /gcc | |
| parent | 1f0dc22ab5f61ed6b91118f946879dac3e7c9a67 (diff) | |
| download | gcc-08266db93f51f2bf4fe3a211c2f9f4bf1875f725.zip gcc-08266db93f51f2bf4fe3a211c2f9f4bf1875f725.tar.gz gcc-08266db93f51f2bf4fe3a211c2f9f4bf1875f725.tar.bz2 | |
i386: Emulate MMX mulv4hi3 with SSE
Emulate MMX mulv4hi3 with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_mulv4hi3): Also allow
TARGET_MMX_WITH_SSE.
(mulv4hi3): New.
(*mmx_mulv4hi3): Also allow TARGET_MMX_WITH_SSE. Add SSE
support.
From-SVN: r271218
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 9 | ||||
| -rw-r--r-- | gcc/config/i386/mmx.md | 32 |
2 files changed, 31 insertions, 10 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3449547..db75ab4 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,6 +1,15 @@ 2019-05-15 H.J. Lu <hongjiu.lu@intel.com> PR target/89021 + * config/i386/mmx.md (mmx_mulv4hi3): Also allow + TARGET_MMX_WITH_SSE. + (mulv4hi3): New. + (*mmx_mulv4hi3): Also allow TARGET_MMX_WITH_SSE. Add SSE + support. + +2019-05-15 H.J. Lu <hongjiu.lu@intel.com> + + PR target/89021 * config/i386/mmx.md (MMXMODEI8): Require TARGET_SSE2 for V1DI. (plusminus:mmx_<plusminus_insn><mode>3): Check TARGET_MMX_WITH_SSE. diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index d0dcd2f..b51f3ac 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -741,19 +741,31 @@ (define_expand "mmx_mulv4hi3" [(set (match_operand:V4HI 0 "register_operand") - (mult:V4HI (match_operand:V4HI 1 "nonimmediate_operand") - (match_operand:V4HI 2 "nonimmediate_operand")))] - "TARGET_MMX" + (mult:V4HI (match_operand:V4HI 1 "register_mmxmem_operand") + (match_operand:V4HI 2 "register_mmxmem_operand")))] + "TARGET_MMX || TARGET_MMX_WITH_SSE" + "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);") + +(define_expand "mulv4hi3" + [(set (match_operand:V4HI 0 "register_operand") + (mult:V4HI (match_operand:V4HI 1 "register_operand") + (match_operand:V4HI 2 "register_operand")))] + "TARGET_MMX_WITH_SSE" "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);") (define_insn "*mmx_mulv4hi3" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (mult:V4HI (match_operand:V4HI 1 "nonimmediate_operand" "%0") - (match_operand:V4HI 2 "nonimmediate_operand" "ym")))] - "TARGET_MMX && ix86_binary_operator_ok (MULT, V4HImode, operands)" - "pmullw\t{%2, %0|%0, %2}" - [(set_attr "type" "mmxmul") - (set_attr "mode" "DI")]) + [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yv") + (mult:V4HI (match_operand:V4HI 1 "register_mmxmem_operand" "%0,0,Yv") + (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yv")))] + "(TARGET_MMX || TARGET_MMX_WITH_SSE) + && ix86_binary_operator_ok (MULT, V4HImode, operands)" + "@ + pmullw\t{%2, %0|%0, %2} + pmullw\t{%2, %0|%0, %2} + vpmullw\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "mmxmul,ssemul,ssemul") + (set_attr "mode" "DI,TI,TI")]) (define_expand "mmx_smulv4hi3_highpart" [(set (match_operand:V4HI 0 "register_operand") |