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author | Michael Hayes <m.hayes@elec.canterbury.ac.nz> | 1999-01-15 15:46:01 +0000 |
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committer | Michael Hayes <m.hayes@gcc.gnu.org> | 1999-01-15 15:46:01 +0000 |
commit | 077613ba4547428a8173568eda7fb3ae6527d740 (patch) | |
tree | ac9741e191a7a3810ff5d9da0639521096de38a0 /gcc | |
parent | cce88d8642ab0293eb36de9594c46666241440fd (diff) | |
download | gcc-077613ba4547428a8173568eda7fb3ae6527d740.zip gcc-077613ba4547428a8173568eda7fb3ae6527d740.tar.gz gcc-077613ba4547428a8173568eda7fb3ae6527d740.tar.bz2 |
c4x.md (not_repeat_reg): Allow ldp instruction in delay slot of RPTBD.
* config/c4x/c4x.md (not_repeat_reg): Allow ldp instruction
in delay slot of RPTBD.
From-SVN: r24682
Diffstat (limited to 'gcc')
-rw-r--r-- | gcc/ChangeLog | 10 | ||||
-rw-r--r-- | gcc/config/c4x/c4x.md | 5 |
2 files changed, 14 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1df7421..bb0b57c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +Sat Jan 16 12:47:15 1999 Michael Hayes <m.hayes@elec.canterbury.ac.nz> + + * config/c4x/c4x.md (not_repeat_reg): Allow ldp instruction + in delay slot of RPTBD. + +Sat Jan 16 12:26:40 1999 Michael Hayes <m.hayes@elec.canterbury.ac.nz> + + * config/c4x/libgcc.S (___divhi3, ___modhi3): Fix long long + divide and modulo sign problem. + Fri Jan 15 11:02:31 1999 Michael Hayes <m.hayes@elec.canterbury.ac.nz> * unroll.c (loop_iterations): Return 0 if the last loop insn diff --git a/gcc/config/c4x/c4x.md b/gcc/config/c4x/c4x.md index 50c1a32..7d85854 100644 --- a/gcc/config/c4x/c4x.md +++ b/gcc/config/c4x/c4x.md @@ -342,7 +342,7 @@ (const_string "false"))) (define_attr "not_repeat_reg" "false,true" - (cond [(eq_attr "type" "unary,unarycc,compare,lda,store") + (cond [(eq_attr "type" "unary,unarycc,compare,lda,ldp,store") (if_then_else (and (match_operand 0 "not_rc_reg" "") (match_operand 1 "not_rc_reg" "")) (const_string "true") (const_string "false")) @@ -353,6 +353,9 @@ (const_string "true") (const_string "false"))] (const_string "false"))) +/* Disable compare because the c4x contains a bug. The cmpi insn sets the CC + in the read phase of the pipeline instead of the execution phase when + two registers are compared. */ (define_attr "in_annul_slot_1" "false,true" (if_then_else (and (and (eq_attr "cpu" "c4x") (eq_attr "type" "!jump,call,rets,jmpc,compare,db,dbc,repeat,repeat_top,laj,push,pop,lda,ldp,multi")) |