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| author | Juzhe-Zhong <juzhe.zhong@rivai.ai> | 2023-05-24 15:31:46 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2023-05-24 15:31:46 +0800 |
| commit | ec40410d98e57fc6650241d4e05119a1f0af6a41 (patch) | |
| tree | a8b7857f20be4749083f0fdddae1da43be97016e /gcc/value-range.h | |
| parent | d03da468b263f46e537a8c785ba8e6d4ce41608c (diff) | |
| download | gcc-ec40410d98e57fc6650241d4e05119a1f0af6a41.zip gcc-ec40410d98e57fc6650241d4e05119a1f0af6a41.tar.gz gcc-ec40410d98e57fc6650241d4e05119a1f0af6a41.tar.bz2 | |
RISC-V: Add RVV mask logic auto-vectorization
This patch is adding mask logic auto-vectorization, define the pattern
as "define_insn_and_split" to allow combine PASS easily combine series
instructions.
For example:
combine vmxor.mm + vmnot.m into vmxnor.mm
Signed-off-by: Juzhe-Zhong <juzhe.zhong@rivai.ai>
gcc/ChangeLog:
* config/riscv/autovec.md (<optab><mode>3): New pattern.
(one_cmpl<mode>2): Ditto.
(*<optab>not<mode>): Ditto.
(*n<optab><mode>): Ditto.
* config/riscv/riscv-v.cc (expand_vec_cmp_float): Change to
one_cmpl.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/cmp/vcond-4.c: New test.
* gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c: New test.
Diffstat (limited to 'gcc/value-range.h')
0 files changed, 0 insertions, 0 deletions