RISC-V: Support RVV VFWSUB rounding mode intrinsic API

This patch would like to support the rounding mode API for the VFWSUB
for the below samples.

    * __riscv_vfwsub_vv_f64m2_rm
    * __riscv_vfwsub_vv_f64m2_rm_m
    * __riscv_vfwsub_vf_f64m2_rm
    * __riscv_vfwsub_vf_f64m2_rm_m
    * __riscv_vfwsub_wv_f64m2_rm
    * __riscv_vfwsub_wv_f64m2_rm_m
    * __riscv_vfwsub_wf_f64m2_rm
    * __riscv_vfwsub_wf_f64m2_rm_m

Signed-off-by: Pan Li <pan2.li@intel.com>

gcc/ChangeLog:

	* config/riscv/riscv-vector-builtins-bases.cc (BASE): Add
	vfwsub frm.
	* config/riscv/riscv-vector-builtins-bases.h: Add declaration.
	* config/riscv/riscv-vector-builtins-functions.def (vfwsub_frm):
	Add vfwsub function definitions.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/float-point-widening-sub.c: New test.

0 files changed, 0 insertions, 0 deletions