RISC-V: Support RVV VFMUL rounding mode intrinsic API

Update in v2:

* Sync with upstream for the vfmul duplicated declaration.

Original log:

This patch would like to support the rounding mode API for the VFMUL
for the below samples.

* __riscv_vfmul_vv_f32m1_rm
* __riscv_vfmul_vv_f32m1_rm_m
* __riscv_vfmul_vf_f32m1_rm
* __riscv_vfmul_vf_f32m1_rm_m

Signed-off-by: Pan Li <pan2.li@intel.com>

gcc/ChangeLog:

	* config/riscv/riscv-vector-builtins-bases.cc
	(vfmul_frm_obj): New declaration.
	(Base): Likewise.
	* config/riscv/riscv-vector-builtins-bases.h: Likewise.
	* config/riscv/riscv-vector-builtins-functions.def
	(vfmul_frm): New function definition.
	* config/riscv/vector.md: Add vfmul to frm_mode.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/float-point-single-mul.c: New test.

0 files changed, 0 insertions, 0 deletions