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| author | zhongjuzhe <juzhe.zhong@rivai.ai> | 2022-08-27 19:07:56 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2022-08-29 10:16:06 +0800 |
| commit | 31380d4b7925912b9c34afe8cdb8dffe6cd50b94 (patch) | |
| tree | ecd116c6a4a85decbbe5080821878ccc021a35dd /gcc/value-range.cc | |
| parent | b842690086b588349637125c114d5fdcbb79531f (diff) | |
| download | gcc-31380d4b7925912b9c34afe8cdb8dffe6cd50b94.zip gcc-31380d4b7925912b9c34afe8cdb8dffe6cd50b94.tar.gz gcc-31380d4b7925912b9c34afe8cdb8dffe6cd50b94.tar.bz2 | |
RISC-V: Add RVV registers
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_v_ext_vector_mode_p): New function.
(riscv_classify_address): Disallow PLUS/LO_SUM/CONST_INT address types for RVV.
(riscv_address_insns): Add RVV modes condition.
(riscv_binary_cost): Ditto.
(riscv_rtx_costs): Adjust cost for RVV.
(riscv_secondary_memory_needed): Add RVV modes condition.
(riscv_hard_regno_nregs): Add RVV register allocation.
(riscv_hard_regno_mode_ok): Add RVV register allocation.
(riscv_class_max_nregs): Add RVV register allocation.
* config/riscv/riscv.h (DWARF_FRAME_REGNUM): Add VL/VTYPE and vector registers in Dwarf.
(UNITS_PER_V_REG): New macro.
(FIRST_PSEUDO_REGISTER): Adjust first pseudo num for RVV.
(V_REG_FIRST): New macro.
(V_REG_LAST): Ditto.
(V_REG_NUM): Ditto.
(V_REG_P): Ditto.
(VL_REG_P): Ditto.
(VTYPE_REG_P): Ditto.
(RISCV_DWARF_VL): Ditto.
(RISCV_DWARF_VTYPE): Ditto.
(enum reg_class): Add RVV register types.
(REG_CLASS_CONTENTS): Add RVV register types.
* config/riscv/riscv.md: Add VL/VTYPE register number constants.
Diffstat (limited to 'gcc/value-range.cc')
0 files changed, 0 insertions, 0 deletions