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| author | Ju-Zhe Zhong <juzhe.zhong@rivai.ai> | 2022-10-10 21:43:22 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2022-10-11 09:39:43 +0800 |
| commit | 1627d05240da3b1a985b1b2006b7a9f562fe9d43 (patch) | |
| tree | 8319200da42f74401f93e21aa1c24c166f2927ab /gcc/value-range.cc | |
| parent | 27bfe54e975d12aac750f0702f716a4c1c0a81fe (diff) | |
| download | gcc-1627d05240da3b1a985b1b2006b7a9f562fe9d43.zip gcc-1627d05240da3b1a985b1b2006b7a9f562fe9d43.tar.gz gcc-1627d05240da3b1a985b1b2006b7a9f562fe9d43.tar.bz2 | |
RISC-V: Add missing vsetvl instruction type.
When implementing built-in framework, I notice I missed
vsetvl instruction type, so add it in a single patch
preparing for the following patches.
gcc/ChangeLog:
* config/riscv/riscv.md: Add vsetvl instruction type.
Reviewed-by: Kito Cheng <kito.cheng@sifive.com>
Diffstat (limited to 'gcc/value-range.cc')
0 files changed, 0 insertions, 0 deletions