RISC-V: Refactor the framework of RVV auto-vectorization

This patch is to refactor the framework of RVV auto-vectorization.
Since we find out are keep adding helpers && wrappers when implementing
auto-vectorization.
It will make the RVV auto-vectorizaiton very messy.

After double check my downstream RVV GCC, assemble all auto-vectorization
patterns we are going to have. Base on these informations, I refactor the
RVV framework to make it is easier and flexible for future use.

For example, we will definitely implement len_mask_load/len_mask_store
patterns which have both length && mask operand and use undefine merge operand.

len_cond_div or cond_div will have length or mask operand and use a real
merge operand instead of undefine merge operand.

Also, we will have some patterns will use tail undisturbed and mask any.

etc..... We will defintely have various features.

Base on these circumstances, we add these following private members:

  int m_op_num;
  /* It't true when the pattern has a dest operand. Most of the patterns have
     dest operand wheras some patterns like STOREs does not have dest
     operand.
  */
  bool m_has_dest_p;
  bool m_fully_unmasked_p;
  bool m_use_real_merge_p;
  bool m_has_avl_p;
  bool m_vlmax_p;
  bool m_has_tail_policy_p;
  bool m_has_mask_policy_p;
  enum tail_policy m_tail_policy;
  enum mask_policy m_mask_policy;
  machine_mode m_dest_mode;
  machine_mode m_mask_mode;

These variables I believe can cover all potential situations.

And the instruction generater wrapper is "emit_insn" which will add
operands and
emit instruction according to the variables I mentioned above.

After this is done. We will easily add helpers without changing any base
class "insn_expand".

Currently, we have "emit_vlmax_tany_many" and "emit_nonvlmax_tany_many".

For example, when we want to emit a binary operations:
We have

Then just use emit_vlmax_tany_many (...RVV_BINOP_NUM...)

So, if we support ternary operation in the future. It's quite simple:
emit_vlmax_tany_many (...RVV_BINOP_NUM...)

"*_tany_many" means we are using tail any and mask any.

We will definitely need tail undisturbed or mask undisturbed when we
support these patterns
in middle-end. It's very simple to extend such helper base on current
framework:

we can do that in the future like this:

void
emit_nonvlmax_tu_mu (unsigned icode, int op_num, rtx *ops)
{
  machine_mode data_mode = GET_MODE (ops[0]);
  machine_mode mask_mode = get_mask_mode (data_mode).require ();
  /* The number = 11 is because we have maximum 11 operands for
     RVV instruction patterns according to vector.md.  */
  insn_expander<11> e (/*OP_NUM*/ op_num,
		       /*HAS_DEST_P*/ true,
		       /*USE_ALL_TRUES_MASK_P*/ true,
		       /*USE_UNDEF_MERGE_P*/ true,
		       /*HAS_AVL_P*/ true,
		       /*VLMAX_P*/ false,
		       /*HAS_TAIL_POLICY_P*/ true,
		       /*HAS_MASK_POLICY_P*/ true,
		       /*TAIL_POLICY*/ TAIL_UNDISTURBED,
		       /*MASK_POLICY*/ MASK_UNDISTURBED,
		       /*DEST_MODE*/ data_mode,
		       /*MASK_MODE*/ mask_mode);
  e.emit_insn ((enum insn_code) icode, ops);
}

That's enough (I have tested it fully in my downstream RVV GCC).
I didn't add it in this patch.

Thanks.

Signed-off-by: Juzhe-Zhong <juzhe.zhong@rivai.ai>

gcc/ChangeLog:

	* config/riscv/autovec.md: Refactor the framework of RVV auto-vectorization.
	* config/riscv/riscv-protos.h (RVV_MISC_OP_NUM): Ditto.
	(RVV_UNOP_NUM): New macro.
	(RVV_BINOP_NUM): Ditto.
	(legitimize_move): Refactor the framework of RVV auto-vectorization.
	(emit_vlmax_op): Ditto.
	(emit_vlmax_reg_op): Ditto.
	(emit_len_op): Ditto.
	(emit_len_binop): Ditto.
	(emit_vlmax_tany_many): Ditto.
	(emit_nonvlmax_tany_many): Ditto.
	(sew64_scalar_helper): Ditto.
	(expand_tuple_move): Ditto.
	* config/riscv/riscv-v.cc (emit_pred_op): Ditto.
	(emit_pred_binop): Ditto.
	(emit_vlmax_op): Ditto.
	(emit_vlmax_tany_many): New function.
	(emit_len_op): Remove.
	(emit_nonvlmax_tany_many): New function.
	(emit_vlmax_reg_op): Remove.
	(emit_len_binop): Ditto.
	(emit_index_op): Ditto.
	(expand_vec_series): Refactor the framework of RVV auto-vectorization.
	(expand_const_vector): Ditto.
	(legitimize_move): Ditto.
	(sew64_scalar_helper): Ditto.
	(expand_tuple_move): Ditto.
	(expand_vector_init_insert_elems): Ditto.
	* config/riscv/riscv.cc (vector_zero_call_used_regs): Ditto.
	* config/riscv/vector.md: Ditto.

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