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| author | Christophe Lyon <christophe.lyon@arm.com> | 2023-02-07 19:26:29 +0000 |
|---|---|---|
| committer | Christophe Lyon <christophe.lyon@arm.com> | 2023-05-03 16:58:29 +0200 |
| commit | 3fe5a244f55f7764bda5852a45ecbe9b3e0bab81 (patch) | |
| tree | 99c0eea5ddbfebf4b59d27cbf0aebfc82120e440 /gcc/value-range.cc | |
| parent | a7cbd5f9a8e79741f33f6af9ff8a6d5610fa17c1 (diff) | |
| download | gcc-3fe5a244f55f7764bda5852a45ecbe9b3e0bab81.zip gcc-3fe5a244f55f7764bda5852a45ecbe9b3e0bab81.tar.gz gcc-3fe5a244f55f7764bda5852a45ecbe9b3e0bab81.tar.bz2 | |
arm: [MVE intrinsics] factorize several binary operations
Factorize vabdq, vhaddq, vhsubq, vmulhq, vqaddq_u, vqdmulhq,
vqrdmulhq, vqrshlq, vqshlq, vqsubq_u, vrhaddq, vrmulhq, vrshlq
so that they use the same pattern.
2022-09-08 Christophe Lyon <christophe.lyon@arm.com>
gcc/
* config/arm/iterators.md (MVE_INT_SU_BINARY): New.
(mve_insn): Add vabdq, vhaddq, vhsubq, vmulhq, vqaddq, vqdmulhq,
vqrdmulhq, vqrshlq, vqshlq, vqsubq, vrhaddq, vrmulhq, vrshlq.
(supf): Add VQDMULHQ_S, VQRDMULHQ_S.
* config/arm/mve.md (mve_vabdq_<supf><mode>)
(@mve_vhaddq_<supf><mode>, mve_vhsubq_<supf><mode>)
(mve_vmulhq_<supf><mode>, mve_vqaddq_<supf><mode>)
(mve_vqdmulhq_s<mode>, mve_vqrdmulhq_s<mode>)
(mve_vqrshlq_<supf><mode>, mve_vqshlq_<supf><mode>)
(mve_vqsubq_<supf><mode>, @mve_vrhaddq_<supf><mode>)
(mve_vrmulhq_<supf><mode>, mve_vrshlq_<supf><mode>): Merge into
...
(@mve_<mve_insn>q_<supf><mode>): ... this.
* config/arm/vec-common.md (avg<mode>3_floor, uavg<mode>3_floor)
(avg<mode>3_ceil, uavg<mode>3_ceil): Use gen_mve_q instead of
gen_mve_vhaddq / gen_mve_vrhaddq.
Diffstat (limited to 'gcc/value-range.cc')
0 files changed, 0 insertions, 0 deletions