RISC-V: Support vfwmul.vv combine lowering

Consider the following complicate case:
  __attribute__ ((noipa)) void vwadd_##TYPE1_##TYPE2 (                         \
    TYPE1 *__restrict dst, TYPE1 *__restrict dst2, TYPE1 *__restrict dst3,     \
    TYPE1 *__restrict dst4, TYPE2 *__restrict a, TYPE2 *__restrict b,          \
    TYPE2 *__restrict a2, TYPE2 *__restrict b2, int n)                         \
  {                                                                            \
    for (int i = 0; i < n; i++)                                                \
      {                                                                        \
	dst[i] = (TYPE1) a[i] * (TYPE1) b[i];                                  \
	dst2[i] = (TYPE1) a2[i] * (TYPE1) b[i];                                \
	dst3[i] = (TYPE1) a2[i] * (TYPE1) a[i];                                \
	dst4[i] = (TYPE1) a[i] * (TYPE1) b2[i];                                \
      }                                                                        \
  }

TEST_TYPE (double, float)

Such complicate situation, Combine PASS can not combine extension of both operands on the fly.
So the combine PASS will first try to combine one of the combine extension, and then combine
the other. The combine flow is as follows:

Original IR:
(set (reg 0) (float_extend: (reg 1))
(set (reg 3) (float_extend: (reg 2))
(set (reg 4) (mult: (reg 0) (reg 3))

First step of combine:
(set (reg 3) (float_extend: (reg 2))
(set (reg 4) (mult: (float_extend: (reg 1) (reg 3))

Second step of combine:
(set (reg 4) (mult: (float_extend: (reg 1) (float_extend: (reg 2))

So, to enhance the combine optimization, we add a "pseudo vwfmul.wv" RTL pattern in autovec-opt.md
which is (set (reg 0) (mult (float_extend (reg 1) (reg 2)))).

gcc/ChangeLog:

	* config/riscv/autovec-opt.md (@pred_single_widen_mul<any_extend:su><mode>): Change "@"
	into "*" in pattern name which simplifies build files.
	(*pred_single_widen_mul<any_extend:su><mode>): Ditto.
	(*pred_single_widen_mul<mode>): New pattern.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/widen/widen-3.c: Add floating-point.
	* gcc.target/riscv/rvv/autovec/widen/widen-7.c: Ditto.
	* gcc.target/riscv/rvv/autovec/widen/widen-complicate-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/widen/widen_run-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/widen/widen_run-7.c: Ditto.
	* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-3.c: New test.
	* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-7.c: New test.

0 files changed, 0 insertions, 0 deletions