aboutsummaryrefslogtreecommitdiff
path: root/gcc/tree.h
diff options
context:
space:
mode:
authorMichael Meissner <meissner@linux.ibm.com>2022-03-29 13:14:43 -0400
committerMichael Meissner <meissner@linux.ibm.com>2022-03-29 13:17:05 -0400
commit9f9ccc4a5788fc6afbb4fb2d56ad20dde28f0de5 (patch)
tree100b9525b8becb2aa68fbb723b25645439b0f6c8 /gcc/tree.h
parentb243ad1afb7f06ef4ab7649600d900b09b9c6b52 (diff)
downloadgcc-9f9ccc4a5788fc6afbb4fb2d56ad20dde28f0de5.zip
gcc-9f9ccc4a5788fc6afbb4fb2d56ad20dde28f0de5.tar.gz
gcc-9f9ccc4a5788fc6afbb4fb2d56ad20dde28f0de5.tar.bz2
Allow vsx_extract_<mode> to use Altivec registers.
I noticed that the vsx_extract_<mode> pattern for V2DImode and V2DFmode only allowed traditional floating point registers, and it did not allow Altivec registers. The original code was written a few years ago when we used the old register allocator, and support for scalar floating point in Altivec registers was just being added to GCC. I have built the spec 2017 benchmark suite With all 4 patches in this series applied, and compared it to the build with the previous 3 patches applied. In addition to the changes from the previous 3 patches, this patch now changes the code for the following 3 benchmarks (2 floating point, 1 integer): bwaves_r, fotonik3d_r, xalancbmk_r I have built bootstrap versions on the following systems. There were no regressions in the runs: Power9 little endian, --with-cpu=power9 Power10 little endian, --with-cpu=power10 Power8 big endian, --with-cpu=power8 (both 32-bit & 64-bit tests) 2022-03-29 Michael Meissner <meissner@linux.ibm.com> gcc/ * config/rs6000/vsx.md (vsx_extract_<mode>): Allow destination to be any VSX register.
Diffstat (limited to 'gcc/tree.h')
0 files changed, 0 insertions, 0 deletions