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| author | Tom de Vries <tdevries@suse.de> | 2022-01-26 14:16:42 +0100 |
|---|---|---|
| committer | Tom de Vries <tdevries@suse.de> | 2022-02-01 19:28:48 +0100 |
| commit | 57f971f99209cc950d7e706b7b52f4c9ef1d10b0 (patch) | |
| tree | 18dbffcb88d4a184356cf9e98e66f0a0844fc353 /gcc/tree.h | |
| parent | 456de10c549379b74d4858f00d4b8817035a73fc (diff) | |
| download | gcc-57f971f99209cc950d7e706b7b52f4c9ef1d10b0.zip gcc-57f971f99209cc950d7e706b7b52f4c9ef1d10b0.tar.gz gcc-57f971f99209cc950d7e706b7b52f4c9ef1d10b0.tar.bz2 | |
[nvptx] Update bar.sync for ptx isa 6.0
In ptx isa 6.0, a new barrier instruction was added, and bar.sync was
redefined as barrier.sync.aligned.
The aligned modifier indicates that all threads in a CTA will execute the same
barrier instruction.
The seems fine for a form "bar.sync 0".
But a "bar.sync %rx,64" (as used for vector length > 32) may execute a
diffferent barrier depending on the value of %rx, so we can't assume it's
aligned.
Fix this by using "barrier.sync %rx,64" instead.
Tested on x86_64 with nvptx accelerator.
gcc/ChangeLog:
2022-01-27 Tom de Vries <tdevries@suse.de>
* config/nvptx/nvptx-opts.h (enum ptx_version): Add PTX_VERSION_6_0.
* config/nvptx/nvptx.h (TARGET_PTX_6_0): New macro.
* config/nvptx/nvptx.md (define_insn "nvptx_barsync"): Use barrier
insn for TARGET_PTX_6_0.
Diffstat (limited to 'gcc/tree.h')
0 files changed, 0 insertions, 0 deletions