aboutsummaryrefslogtreecommitdiff
path: root/gcc/tree.c
diff options
context:
space:
mode:
authorRichard Earnshaw <rearnsha@arm.com>2019-10-18 19:03:27 +0000
committerRichard Earnshaw <rearnsha@gcc.gnu.org>2019-10-18 19:03:27 +0000
commit5899656b61231cc0e2dac4d7a58fab58674ba344 (patch)
tree046cab757eff2ab960fd3733a3d1e35630c3bacf /gcc/tree.c
parent0b478cddf9e95406cd865c94bf99705ec8acddde (diff)
downloadgcc-5899656b61231cc0e2dac4d7a58fab58674ba344.zip
gcc-5899656b61231cc0e2dac4d7a58fab58674ba344.tar.gz
gcc-5899656b61231cc0e2dac4d7a58fab58674ba344.tar.bz2
[arm] Early split simple DImode equality comparisons
This is the first step of early splitting all the DImode comparison operations. We start by factoring the DImode handling out of arm_gen_compare_reg into its own function. Simple DImode equality comparisions (such as equality with zero, or equality with a constant that is zero in one of the two word values that it comprises) can be done using a single subtract followed by an ORRS instruction. This avoids the need for conditional execution. For example, (r0 != 5) can be written as SUB Rt, R0, #5 ORRS Rt, Rt, R1 The ORRS is now expanded using an SImode pattern that already exists in the MD file and this gives the register allocator more freedom to select registers (consecutive pairs are no-longer required). Furthermore, we can then delete the arm_cmpdi_zero pattern as it is no-longer required. We use SUB for the value adjustment as this has a generally more flexible range of immediates than XOR and what's more has the opportunity to be relaxed in thumb2 to a 16-bit SUBS instruction. * config/arm/arm.c (arm_select_cc_mode): For DImode equality tests return CC_Zmode if comparing against a constant where one word is zero. (arm_gen_compare_reg): Split DImode handling to ... (arm_gen_dicompare_reg): ... here. Handle equality comparisons against simple constants. * config/arm/arm.md (arm_cmpdi_zero): Delete pattern. From-SVN: r277177
Diffstat (limited to 'gcc/tree.c')
0 files changed, 0 insertions, 0 deletions