RISC-V: Support neg VLS auto-vectorization

#include "riscv_vector.h"

#define DEF_OP_V(PREFIX, NUM, TYPE, OP)                                        \
  void __attribute__ ((noinline, noclone))                                     \
  PREFIX##_##TYPE##NUM (TYPE *restrict a, TYPE *restrict b)                    \
  {                                                                            \
    for (int i = 0; i < NUM; ++i)                                              \
      a[i] = OP b[i];                                                          \
  }

DEF_OP_V (neg, 16, int32_t, -)

After this patch:

neg_int32_t16:
	vsetivli	zero,16,e32,mf2,ta,ma
	vle32.v	v1,0(a1)
	vneg.v	v1,v1
	vse32.v	v1,0(a0)
	ret

gcc/ChangeLog:

	* config/riscv/autovec-vls.md (<optab><mode>2): Add VLS neg.
	* config/riscv/vector.md: Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vls/def.h: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/neg-1.c: New test.

0 files changed, 0 insertions, 0 deletions