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| author | liuhongt <hongtao.liu@intel.com> | 2020-08-13 14:20:43 +0800 |
|---|---|---|
| committer | liuhongt <hongtao.liu@intel.com> | 2020-08-21 12:48:41 +0800 |
| commit | 388cb292a94f98a276548cd6ce01285cf36d17df (patch) | |
| tree | 86f0ece0f54c07db71a0fafb813f8809004fc97f /gcc/tree-vectorizer.h | |
| parent | 16516644d8f5c13e666251470d604778d347f796 (diff) | |
| download | gcc-388cb292a94f98a276548cd6ce01285cf36d17df.zip gcc-388cb292a94f98a276548cd6ce01285cf36d17df.tar.gz gcc-388cb292a94f98a276548cd6ce01285cf36d17df.tar.bz2 | |
Enable bitwise operation for type mask.
Enable operator or/xor/and/andn/not for mask register, kxnor is not
enabled since there's no corresponding instruction for general
registers.
gcc/
PR target/88808
* config/i386/i386.c (ix86_preferred_reload_class): Allow
QImode data go into mask registers.
* config/i386/i386.md: (*movhi_internal): Adjust constraints
for mask registers.
(*movqi_internal): Ditto.
(*anddi_1): Support mask register operations
(*and<mode>_1): Ditto.
(*andqi_1): Ditto.
(*andn<mode>_1): Ditto.
(*<code><mode>_1): Ditto.
(*<code>qi_1): Ditto.
(*one_cmpl<mode>2_1): Ditto.
(*one_cmplsi2_1_zext): Ditto.
(*one_cmplqi2_1): Ditto.
(define_peephole2): Move constant 0/-1 directly into mask
registers.
* config/i386/predicates.md (mask_reg_operand): New predicate.
* config/i386/sse.md (define_split): Add post-reload splitters
that would convert "generic" patterns to mask patterns.
(*knotsi_1_zext): New define_insn.
gcc/testsuite/
* gcc.target/i386/bitwise_mask_op-1.c: New test.
* gcc.target/i386/bitwise_mask_op-2.c: New test.
* gcc.target/i386/bitwise_mask_op-3.c: New test.
* gcc.target/i386/avx512bw-pr88465.c: New testcase.
* gcc.target/i386/avx512bw-kunpckwd-1.c: Adjust testcase.
* gcc.target/i386/avx512bw-kunpckwd-3.c: Ditto.
* gcc.target/i386/avx512dq-kmovb-5.c: Ditto.
* gcc.target/i386/avx512f-kmovw-5.c: Ditto.
* gcc.target/i386/pr55342.c: Ditto.
Diffstat (limited to 'gcc/tree-vectorizer.h')
0 files changed, 0 insertions, 0 deletions