RISC-V: Add testcases for form 4 of unsigned vector .SAT_ADD IMM

This patch would like to add test cases for the unsigned vector .SAT_ADD
when one of the operand is IMM.

Form 4:
  #define DEF_VEC_SAT_U_ADD_IMM_FMT_4(T, IMM)                               \
  T __attribute__((noinline))                                               \
  vec_sat_u_add_imm##IMM##_##T##_fmt_4 (T *out, T *in, unsigned limit)      \
  {                                                                         \
    unsigned i;                                                             \
    T ret;                                                                  \
    for (i = 0; i < limit; i++)                                             \
      {                                                                     \
        out[i] = __builtin_add_overflow (in[i], IMM, &ret) == 0 ? ret : -1; \
      }                                                                     \
  }

DEF_VEC_SAT_U_ADD_IMM_FMT_4(uint64_t, 123)

The below test are passed for this patch.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vec_sat_arith.h: Add test helper macros.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-13.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-14.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-15.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-16.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-13.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-14.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-15.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-16.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

0 files changed, 0 insertions, 0 deletions