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| author | Kewen Lin <linkw@linux.ibm.com> | 2024-11-21 07:41:33 +0000 |
|---|---|---|
| committer | Kewen Lin <linkw@gcc.gnu.org> | 2024-11-21 07:41:33 +0000 |
| commit | 2441dc2495d257c4894a4d0c8d36cfbdc851579c (patch) | |
| tree | c4c636df0f38995b15d6613d46d1a29e77a1c587 /gcc/tree-vectorizer.h | |
| parent | 0719ade048d66c91eebdcce07ae69e90a8385e1e (diff) | |
| download | gcc-2441dc2495d257c4894a4d0c8d36cfbdc851579c.zip gcc-2441dc2495d257c4894a4d0c8d36cfbdc851579c.tar.gz gcc-2441dc2495d257c4894a4d0c8d36cfbdc851579c.tar.bz2 | |
rs6000: Add veqv support to *eqv<mode>3_internal1
When making patch to replace TARGET_P8_VECTOR, I noticed
for *eqv<BOOL_128:mode>3_internal1 unlike the other logical
operations, we only exploited the vsx version. I think it
is an oversight, this patch is to consider veqv as well.
gcc/ChangeLog:
* config/rs6000/rs6000.md (*eqv<BOOL_128:mode>3_internal1): Generate
insn veqv if TARGET_ALTIVEC and operands are altivec_register_operand.
Diffstat (limited to 'gcc/tree-vectorizer.h')
0 files changed, 0 insertions, 0 deletions