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author | Pan Li <pan2.li@intel.com> | 2024-06-17 22:31:27 +0800 |
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committer | Pan Li <pan2.li@intel.com> | 2024-06-19 14:09:18 +0800 |
commit | eb549f13fcde079a7bbe27e5ba3d5e80abbffba1 (patch) | |
tree | 412776aa288d7f0c392551cd3dea780f9cf398f7 /gcc/tree-vectorizer.h | |
parent | ed94699eefc7cc8ac8fd79a6d8d81bf05d5a79ff (diff) | |
download | gcc-eb549f13fcde079a7bbe27e5ba3d5e80abbffba1.zip gcc-eb549f13fcde079a7bbe27e5ba3d5e80abbffba1.tar.gz gcc-eb549f13fcde079a7bbe27e5ba3d5e80abbffba1.tar.bz2 |
RISC-V: Add testcases for unsigned .SAT_ADD vector form 8
After the middle-end support the form 8 of unsigned SAT_ADD and
the RISC-V backend implement the .SAT_ADD for vector mode, add
more test case to cover the form 8.
Form 8:
#define DEF_VEC_SAT_U_ADD_FMT_8(T) \
void __attribute__((noinline)) \
vec_sat_u_add_##T##_fmt_8 (T *out, T *op_1, T *op_2, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
{ \
T x = op_1[i]; \
T y = op_2[i]; \
out[i] = x > (T)(x + y) ? -1 : (x + y); \
} \
}
Passed the rv64gcv regression tests.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper
macro for testing.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-29.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-30.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-31.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-32.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
Diffstat (limited to 'gcc/tree-vectorizer.h')
0 files changed, 0 insertions, 0 deletions