RISC-V: Removed unnecessary sign-extend for vsetvl

Hi,

This patch try to combine bellow two insns and then further remove
unnecessary sign_extend operations. This optimization is borrowed
from LLVM (https://godbolt.org/z/4f6v56xej):
  (set (reg:DI 134 [ _1 ])
       (unspec:DI [
               (const_int 19 [0x13])
               (const_int 8 [0x8])
               (const_int 5 [0x5])
               (const_int 2 [0x2]) repeated x2
           ] UNSPEC_VSETVL))
  (set (reg/v:DI 135 [ <retval> ])
          (sign_extend:DI (subreg:SI (reg:DI 134 [ _1 ]) 0)))

The reason we can remove signe_extend is because currently the vl value
returned by the vsetvl instruction ranges from 0 to 65536 (uint16_t), and
bits 17 to 63 (including 31) are always 0, so there is no change after
sign_extend. Note that for HI and QI modes we cannot do this.
Of course, if the range returned by vsetvl later expands to 32 bits,
then this combine pattern needs to be removed. But that could be
a long time from now.

gcc/ChangeLog:

	* config/riscv/vector.md (*vsetvldi_no_side_effects_si_extend):
	New combine pattern.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/vsetvl/vsetvl_int.c: New test.

0 files changed, 0 insertions, 0 deletions