RISC-V: Support RVV VFREC7 rounding mode intrinsic API

Update in v2:

1. Remove the template of vfrec7 frm class.
2. Update the vfrec7_frm_obj declaration.

Original logs:

This patch would like to support the rounding mode API for the
VFREC7 as the below samples.

* __riscv_vfrec7_v_f32m1_rm
* __riscv_vfrec7_v_f32m1_rm_m

Signed-off-by: Pan Li <pan2.li@intel.com>

gcc/ChangeLog:

	* config/riscv/riscv-vector-builtins-bases.cc
	(class vfrec7_frm): New class for frm.
	(vfrec7_frm_obj): New declaration.
	(BASE): Ditto.
	* config/riscv/riscv-vector-builtins-bases.h: Ditto.
	* config/riscv/riscv-vector-builtins-functions.def
	(vfrec7_frm): New intrinsic function definition.
	* config/riscv/vector-iterators.md
	(VFMISC): Remove VFREC7.
	(misc_op): Ditto.
	(float_insn_type): Ditto.
	(VFMISC_FRM): New int iterator.
	(misc_frm_op): New op for frm.
	(float_frm_insn_type): New type for frm.
	* config/riscv/vector.md (@pred_<misc_frm_op><mode>):
	New pattern for misc frm.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/float-point-rec7.c: New test.

0 files changed, 0 insertions, 0 deletions