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authorPan Li <pan2.li@intel.com>2024-06-17 14:53:12 +0800
committerPan Li <pan2.li@intel.com>2024-06-19 14:07:16 +0800
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RISC-V: Add testcases for unsigned .SAT_ADD vector form 3
After the middle-end support the form 3 of unsigned SAT_ADD and the RISC-V backend implement the .SAT_ADD for vector mode, add more test case to cover the form 3. Form 3: #define DEF_VEC_SAT_U_ADD_FMT_3(T) \ void __attribute__((noinline)) \ vec_sat_u_add_##T##_fmt_3 (T *out, T *op_1, T *op_2, unsigned limit) \ { \ unsigned i; \ for (i = 0; i < limit; i++) \ { \ T x = op_1[i]; \ T y = op_2[i]; \ T ret; \ T overflow = __builtin_add_overflow (x, y, &ret); \ out[i] = (T)(-overflow) | ret; \ } \ } Passed the rv64gcv regression tests. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper macro for testing. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-10.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-11.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-12.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-9.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-10.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-11.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-12.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-9.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
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