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| author | Jakub Jelinek <jakub@redhat.com> | 2021-03-19 13:48:44 +0100 |
|---|---|---|
| committer | Jakub Jelinek <jakub@redhat.com> | 2021-03-19 13:48:44 +0100 |
| commit | 009528d61c796608affd1eaa18ae31a3679eb46d (patch) | |
| tree | fcb492d7d60c4f66357bd39cb0049b13678c62ec /gcc/tree-vect-slp-patterns.c | |
| parent | 5cded5aff76c15e48f689842b9aba1d1df5e3c54 (diff) | |
| download | gcc-009528d61c796608affd1eaa18ae31a3679eb46d.zip gcc-009528d61c796608affd1eaa18ae31a3679eb46d.tar.gz gcc-009528d61c796608affd1eaa18ae31a3679eb46d.tar.bz2 | |
arm: Fix mve_vshlq* [PR99593]
As mentioned in the PR, before the r11-6708-gbfab355012ca0f5219da8beb04f2fdaf757d34b7
change v[al]shr<mode>3 expanders were expanding the shifts by register
to gen_ashl<mode>3_{,un}signed which don't support immediate CONST_VECTOR
shift amounts, but now expand to mve_vshlq_<supf><mode> which does.
The testcase ICEs, because the constraint doesn't match the predicate and
because LRA works solely with the constraints, so it can e.g. from REG_EQUAL
propagate there a CONST_VECTOR which matches the constraint but fails the
predicate and only later on other passes will notice the predicate fails
and ICE.
Fixed by adding a constraint that matches the immediate part of the
predicate.
PR target/99593
* config/arm/constraints.md (Ds): New constraint.
* config/arm/vec-common.md (mve_vshlq_<supf><mode>): Use w,Ds
constraint instead of w,Dm.
* g++.target/arm/pr99593.C: New test.
Diffstat (limited to 'gcc/tree-vect-slp-patterns.c')
0 files changed, 0 insertions, 0 deletions