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| author | Pan Li <pan2.li@intel.com> | 2023-06-12 10:45:48 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2023-06-12 11:34:49 +0800 |
| commit | b50b9d369c74b7bd86a2b2beb93877f1e6c253ea (patch) | |
| tree | 7d9c3018d3573a51c77df36742f453ca6e3e9ada /gcc/tree-vect-patterns.cc | |
| parent | 7fc2b9ea2c41ae28154288c0a56e3e5c53b7df5b (diff) | |
| download | gcc-b50b9d369c74b7bd86a2b2beb93877f1e6c253ea.zip gcc-b50b9d369c74b7bd86a2b2beb93877f1e6c253ea.tar.gz gcc-b50b9d369c74b7bd86a2b2beb93877f1e6c253ea.tar.bz2 | |
RISC-V: Add test cases for RVV FP16 undefined and vlmul trunc
This patch would like to add more tests for RVV FP16 undef and vlmul
trunc, aka
__riscv_vundefined_f16*();
__riscv_vlmul_trunc_v_f16*_f16*();
From the user's perspective, it is reasonable to do above operation
when only ZVFHMIN is enabled. This patch would like to add new test
cases to make sure the RVV FP16 vreinterpret works well as expected.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: Add test cases.
* gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Ditto.
Diffstat (limited to 'gcc/tree-vect-patterns.cc')
0 files changed, 0 insertions, 0 deletions