diff options
| author | Pan Li <pan2.li@intel.com> | 2023-06-11 08:28:06 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2023-06-12 11:34:17 +0800 |
| commit | 7fc2b9ea2c41ae28154288c0a56e3e5c53b7df5b (patch) | |
| tree | d83a2ed615953098447cf2a887e8e1abf7559ce6 /gcc/tree-vect-patterns.cc | |
| parent | f47ecca87573244c138a585b2a734e4d7ab5d0a2 (diff) | |
| download | gcc-7fc2b9ea2c41ae28154288c0a56e3e5c53b7df5b.zip gcc-7fc2b9ea2c41ae28154288c0a56e3e5c53b7df5b.tar.gz gcc-7fc2b9ea2c41ae28154288c0a56e3e5c53b7df5b.tar.bz2 | |
RISC-V: Support RVV FP16 MISC vlmul ext intrinsic API
This patch support the intrinsic API of FP16 ZVFHMIN vlmul ext. Aka:
vfloat16*_t <==> vfloat16*_t.
From the user's perspective, it is reasonable to do some type convert
between vfloat16*_t and vfloat16*_t when only ZVFHMIN is enabled.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-types.def
(vfloat16mf4_t): Add type to X2/X4/X8/X16/X32 vlmul ext ops.
(vfloat16mf2_t): Ditto.
(vfloat16m1_t): Ditto.
(vfloat16m2_t): Ditto.
(vfloat16m4_t): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: Add new test cases.
* gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Add new test cases.
Diffstat (limited to 'gcc/tree-vect-patterns.cc')
0 files changed, 0 insertions, 0 deletions