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authorJan Beulich <jbeulich@suse.com>2023-08-07 11:47:27 +0200
committerJan Beulich <jbeulich@suse.com>2023-08-07 11:47:27 +0200
commit31be253e1e07ae33888c2217cb293482921d88c8 (patch)
tree5eb81fc65778e711a154ddd43d962ea71bc1d910 /gcc/tree-vect-patterns.cc
parent0e877fd1b64626bca77395b481f00d65dc442ec3 (diff)
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x86: replace/correct bogus "prefix_extra"
In the rdrand and rdseed cases "prefix_0f" is meant instead. For mmx_floatv2siv2sf2 1 is correct only for the first alternative. For the integer min/max cases 1 uniformly applies to legacy and VEX encodings (the UB and SW variants are dealt with separately anyway). Same for {,V}MOVNTDQA. Unlike {,V}PEXTRW, which has two encoding forms, {,V}PINSRW only has a single form in 0f space. (In *vec_extract<mode> note that the dropped part if the condition also referenced non-existing alternative 2.) Of the integer compare insns, only the 64-bit element forms are encoded in 0f38 space. gcc/ * config/i386/i386.md (@rdrand<mode>): Add "prefix_0f". Drop "prefix_extra". (@rdseed<mode>): Likewise. * config/i386/mmx.md (<code><mode>3 [smaxmin and umaxmin cases]): Adjust "prefix_extra". * config/i386/sse.md (@vec_set<mode>_0): Likewise. (*sse4_1_<code><mode>3<mask_name>): Likewise. (*avx2_eq<mode>3): Likewise. (avx2_gt<mode>3): Likewise. (<sse2p4_1>_pinsr<ssemodesuffix>): Likewise. (*vec_extract<mode>): Likewise. (<vi8_sse4_1_avx2_avx512>_movntdqa): Likewise.
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