diff options
| author | Tamar Christina <tamar.christina@arm.com> | 2024-01-07 17:32:13 +0000 |
|---|---|---|
| committer | Tamar Christina <tamar.christina@arm.com> | 2024-01-07 17:32:13 +0000 |
| commit | d9dd04f9f17e36854387899eb630c64a0c8d1a17 (patch) | |
| tree | a3f614119a64d5431011c39165db76fb52599300 /gcc/tree-vect-loop.cc | |
| parent | 66d82874d2254bcb0124f77e6be220d299eab5f1 (diff) | |
| download | gcc-d9dd04f9f17e36854387899eb630c64a0c8d1a17.zip gcc-d9dd04f9f17e36854387899eb630c64a0c8d1a17.tar.gz gcc-d9dd04f9f17e36854387899eb630c64a0c8d1a17.tar.bz2 | |
arm: Add Advanced SIMD cbranch implementation
This adds an implementation for conditional branch optab for AArch32.
For e.g.
void f1 ()
{
for (int i = 0; i < N; i++)
{
b[i] += a[i];
if (a[i] > 0)
break;
}
}
For 128-bit vectors we generate:
vcgt.s32 q8, q9, #0
vpmax.u32 d7, d16, d17
vpmax.u32 d7, d7, d7
vmov r3, s14 @ int
cmp r3, #0
and of 64-bit vector we can omit one vpmax as we still need to compress to
32-bits.
gcc/ChangeLog:
* config/arm/neon.md (cbranch<mode>4): New.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/vect-early-break_2.c: Skip Arm.
* gcc.dg/vect/vect-early-break_7.c: Likewise.
* gcc.dg/vect/vect-early-break_75.c: Likewise.
* gcc.dg/vect/vect-early-break_77.c: Likewise.
* gcc.dg/vect/vect-early-break_82.c: Likewise.
* gcc.dg/vect/vect-early-break_88.c: Likewise.
* lib/target-supports.exp (add_options_for_vect_early_break,
check_effective_target_vect_early_break_hw,
check_effective_target_vect_early_break): Support AArch32.
* gcc.target/arm/vect-early-break-cbranch.c: New test.
Diffstat (limited to 'gcc/tree-vect-loop.cc')
0 files changed, 0 insertions, 0 deletions