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| author | Tejas Belagod <tejas.belagod@arm.com> | 2024-01-11 12:37:06 +0530 |
|---|---|---|
| committer | Tejas Belagod <tejas.belagod@arm.com> | 2024-02-06 16:04:55 +0530 |
| commit | ca04e7a2e1b08ed02e22e2656ba6032099195856 (patch) | |
| tree | 67be843d856e5c263dc339c94ab5f6076499429f /gcc/tree-vect-loop.cc | |
| parent | c5f48b5fdde849759d0e3b4effd9352a2399d6f9 (diff) | |
| download | gcc-ca04e7a2e1b08ed02e22e2656ba6032099195856.zip gcc-ca04e7a2e1b08ed02e22e2656ba6032099195856.tar.gz gcc-ca04e7a2e1b08ed02e22e2656ba6032099195856.tar.bz2 | |
AArch64: aarch64_class_max_nregs mishandles 64-bit structure modes [PR112577]
The target hook aarch64_class_max_nregs returns the incorrect result for 64-bit
structure modes like V31DImode or V41DFmode etc. The calculation of the nregs
is based on the size of AdvSIMD vector register for 64-bit modes which ought to
be UNITS_PER_VREG / 2. This patch fixes the register size.
gcc/ChangeLog:
PR target/112577
* config/aarch64/aarch64.cc (aarch64_class_max_nregs): Handle 64-bit
vector structure modes correctly.
Diffstat (limited to 'gcc/tree-vect-loop.cc')
0 files changed, 0 insertions, 0 deletions