RISC-V: Refactor prefix [I/L/LL] rounding API autovec iterator

Update in v2:

* Add mode size equal check to disable different mode size when expand,
  because the underlying codegen is not implemented yet.

Original log:

The previous rounding API start with i/l/ll only works on the same
mode types. For example as below, and we arrange the iterator similar
to fcvt.

* SF => SI
* DF => DI

After we refined this limination from middle-end, these API can also
vectorized with different type sizes, aka:

* HF => SI, HF => DI
* SF => DI, SF => SI
* DF => SI, DF => DI

Then the iterator cannot take care of this simply and this patch
would like to re-arrange the iterator in two items.

* V_VLS_F_CONVERT_SI: handle (HF, SF, DF) => SI
* V_VLS_F_CONVERT_DI: handle (HF, SF, DF) => DI

As well as related mode_attr to reconcile the new iterator.

gcc/ChangeLog:

	* config/riscv/autovec.md (lrint<mode><v_i_l_ll_convert>2): Remove.
	(lround<mode><v_i_l_ll_convert>2): Ditto.
	(lceil<mode><v_i_l_ll_convert>2): Ditto.
	(lfloor<mode><v_i_l_ll_convert>2): Ditto.
	(lrint<mode><v_f2si_convert>2): New pattern for cvt from
	FP to SI.
	(lround<mode><v_f2si_convert>2): Ditto.
	(lceil<mode><v_f2si_convert>2): Ditto.
	(lfloor<mode><v_f2si_convert>2): Ditto.
	(lrint<mode><v_f2di_convert>2): New pattern for cvt from
	FP to DI.
	(lround<mode><v_f2di_convert>2): Ditto.
	(lceil<mode><v_f2di_convert>2): Ditto.
	(lfloor<mode><v_f2di_convert>2): Ditto.
	* config/riscv/vector-iterators.md: Renew iterators for both
	the SI and DI.

Signed-off-by: Pan Li <pan2.li@intel.com>

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