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| author | Jin Ma <jinma@linux.alibaba.com> | 2023-11-10 15:14:31 +0800 |
|---|---|---|
| committer | Christoph Müllner <christoph.muellner@vrull.eu> | 2023-11-10 14:26:12 +0100 |
| commit | b70ad8c19aa8be672cdba6afe9cbab2d1254d127 (patch) | |
| tree | 12bcbc9d77bc8cb01fd3522308d8e7a36a3853d3 /gcc/tree-vect-loop.cc | |
| parent | e5f1956498251a4973d52c8aad3faf34d0443169 (diff) | |
| download | gcc-b70ad8c19aa8be672cdba6afe9cbab2d1254d127.zip gcc-b70ad8c19aa8be672cdba6afe9cbab2d1254d127.tar.gz gcc-b70ad8c19aa8be672cdba6afe9cbab2d1254d127.tar.bz2 | |
RISC-V: XTheadMemPair: Fix missing fcsr handling in ISR prologue/epilogue
The t0 register is used as a temporary register for interrupts, so it needs
special treatment. It is necessary to avoid using "th.ldd" in the interrupt
program to stop the subsequent operation of the t0 register, so they need to
exchange positions in the function "riscv_for_each_saved_reg".
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_for_each_saved_reg): Place the interrupt
operation before the XTheadMemPair.
Diffstat (limited to 'gcc/tree-vect-loop.cc')
0 files changed, 0 insertions, 0 deletions